ATmega406 Atmel Corporation, ATmega406 Datasheet - Page 32

• Manufacturer Part Number: ATmega406
• Manufacturer: Atmel Corporation

Specifications of ATmega406

• Flash (kbytes): 40 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 1 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 18
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1.9
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -30 to 85
• I/o Supply Class: 4.0 to 25
• Operating Voltage (vcc): 4.0 to 25
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Pwm Channels: 2
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8.1
8.2
8.3
32
Idle Mode
ADC Noise Reduction Mode
Power-save Mode
ATmega406
• Bit 0 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s
purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of
the SLEEP instruction and to clear it immediately after waking up.
When the SM2:0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode,
stopping the CPU but allowing all peripheral functions to continue operating. This sleep mode
basically halts clk
MCU to wake up from external triggered interrupts as well as internal ones like the Timer Over-
flow interrupt.
When the SM2:0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC
Noise Reduction mode, stopping the CPU but allowing the Voltage ADC (V-ADC), Wake-up
Timer (WUT), Watchdog Timer (WDT), Coulomb Counter (CC), Current Battery Protection
(CBP), Voltage Battery Protection (VBP), Wake-up on Regular Current (WURC), 32 kHz crystal
Oscillator (XOSC_32K) or Slow RC Oscillator (RCOSC_SLOW), the ULTRA Low Power RC
Oscillator (RCOSC_ULP), and the Fast RC Oscillator (RCOSC_FAST) to continue operating.
This sleep mode basically halts clk
This improves the noise environment for the Voltage ADC, enabling higher resolution
measurements.
When the SM2:0 bits are written to 011, the SLEEP instruction makes the MCU enter Power-
save mode. In this mode, the internal Fast RC Oscillator (RCOSC_FAST) is stopped, while
Wake-up Timer (WUT), Watchdog Timer (WDT), Coulomb Counter (CC), Current Battery Pro-
tection (CBP), Voltage Battery Protection (VBP), Wake-up on Regular Current (WURC), 32 kHz
crystal Oscillator (XOSC_32K) or Slow RC Oscillator (RCOSC_SLOW) and the Ultra Low Power
RC Oscillator (RCOSC_ULP) continue operating.
This mode will be the default mode when application software does not require operation of
CPU, Flash or any of the periphery units running at the Fast internal Oscillator (RCOSC_FAST).
If the current through the sense resistor is so small that the Coulomb Counter cannot measure it
accurately, Regular Current detection should be enabled to reduce power consumption. The
WUT keeps accurately track of the time so that battery self discharge can be calculated.
Note that if a level triggered interrupt is used for wake-up from Power-save mode, the changed
level must be held for some time to wake up the MCU. Refer to
for details.
When waking up from Power-save mode, there is a delay from the wake-up condition occurs
until the wake-up becomes effective. This allows the clock to restart and become stable after
having been stopped. The wake-up period is defined in
CPU
and clk
FLASH
, while allowing the other clocks to run. Idle mode enables the
I/O
, clk
CPU
, and clk
FLASH
”Clock Sources” on page
, while allowing the other clocks to run.
”External Interrupts” on page 56
26.
2548E–AVR–07/06