ATmega406 Atmel Corporation, ATmega406 Datasheet - Page 25

• Manufacturer Part Number: ATmega406
• Manufacturer: Atmel Corporation

Specifications of ATmega406

• Flash (kbytes): 40 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 1 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 18
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1.9
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -30 to 85
• I/o Supply Class: 4.0 to 25
• Operating Voltage (vcc): 4.0 to 25
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Pwm Channels: 2
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

7. System Clock and Clock Options
7.1
7.1.1
7.1.2
7.1.3
7.1.4
2548E–AVR–07/06
Clock Systems and their Distribution
CPU Clock – clk
TWI Clock - clk
I/O Clock – clk
Flash Clock – clk
I/O
Figure 7-1
need not be active at a given time. In order to reduce power consumption, the clocks to modules
not being used can be halted by using different sleep modes, as described in
ment and Sleep Modes” on page
Figure 7-1.
The CPU clock is routed to parts of the system concerned with operation of the AVR core.
Examples of such modules are the General Purpose Register File, the Status Register and the
data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing
general operations and calculations.
TWI
The TWI module is provided with a dedicated clock domain. This is because the TWI module
requires a 4 MHz clock to achieve the specified Data Transfer Speed. It also allows power
reduction by halting the clk
match detection in the TWI module is carried out asynchronously when clk
TWI address watch detection in all sleep modes except Power-off.
The I/O clock is used by the majority of the I/O modules. The I/O clock is also used by the Exter-
nal Interrupt module, but note that some external interrupts are detected by asynchronous logic,
allowing such interrupts to be detected even if the I/O clock is halted.
The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul-
taneously with the CPU clock.
CPU
TWI Disconnect
FLASH
Delay
presents the principal clock systems in the AVR and their distribution. All of the clocks
Watchdog Timer
CORE
CPU
Clock Distribution
Battery Protection
Ultra Low Power
clk
& FET Control
RC Oscillator
CPU
RAM
TWI
Reset Logic
clock when TWI communication is not used. Note that address
FLASH and
EEPROM
31. The clock systems are detailed below.
clk
FLASH
Clock Control
AVR
Voltage
ADC
clk
1/4
VADC
Oscillator
Fast RC
Delay
Sync
clk
Other I/O
Modules
I/O
Clock Control
AVR
clk
TWI
TWI
ATmega406
Coulomb Counter
TWI
Oscillator
Slow RC
1/4
clk
ADC
CCADC
0
is halted, enabling
Clock Control
”Power Manage-
Multiplexer
AVR
Clock
32 kHz Crystal
clk
Oscillator
1
WUT
Wake-up
Timer
Run-Time
Selection
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