ATmega406 Atmel Corporation, ATmega406 Datasheet - Page 126

• Manufacturer Part Number: ATmega406
• Manufacturer: Atmel Corporation

Specifications of ATmega406

• Flash (kbytes): 40 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 1 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 18
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1.9
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -30 to 85
• I/o Supply Class: 4.0 to 25
• Operating Voltage (vcc): 4.0 to 25
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Pwm Channels: 2
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

22.2
22.3
22.4
126
Deep Under-voltage Protection
Discharge Over-current Protection
Charge Over-current Protection
ATmega406
The Deep Under-voltage Protection ensures that the battery cells will not be discharged deeper
than the programmable Deep Under-voltage detection level. If the voltage at the VFET pin is
below this level for a time longer than the programmable delay time, C-FET, PC-FET and D-FET
are automatically switched off and the chip enters Power-off mode. The Deep Under-voltage
Early Warning interrupt flag (DUVIF) will be set 250 ms before the chip enters Power-off. This
will give the CPU a chance to take necessary actions before the power is switched off.
The device will remain in the Power-off mode until a charger is connected. When a charger is
detected, a normal power-up sequence is started and the chip initializes to default state.
The Deep Under-voltage delay time and Deep Under-voltage detection level are set in the Bat-
tery Protection Deep Under-voltage Register (BPDUV). The Parameter Registers can be locked
after the initial configuration, prohibiting any further updates until the next Hardware Reset.
Refer to
The Current Battery Protection (CBP) monitors the cell current by sampling the shunt resistor
voltage at the PPI/NNI input pins. A differential operational amplifier amplifies the voltage with a
suitable gain. The output from the operational amplifier is compared to an accurate, programma-
ble On-chip voltage reference by an Analog Comparator. If the shunt resistor voltage is above
the Discharge Over-current Detection level for a time longer than Over-current Protection Reac-
tion Time, the chip activates Discharge Over-current Protection. A sampled system clocked by
the internal ULP Oscillator is used for Over-current and Short-circuit Protection. This ensures a
reliable clock source, off-set cancellation and low power consumption.
When the Discharge Over-current Protection is activated, the external D-FET, PC-FET, and C-
FET are disabled and a Current Protection Timer is started. This timer ensures that the FETs are
disabled for at least one second. The application software must then set the DFE and CFE bits
in the FET Control and Status Register to re-enable normal operation. If the D-FET is re-enabled
while the loading of the battery still is too large, the Discharge Over-current Protection will be
activated again.
If the voltage at the PPI/NNI pins is above the Charge Over-current Detection level for a time
longer than Over-current Protection Reaction Time, the chip activates Charge Over-current
Protection.
When the Charge Over-current Protection is activated, the external D-FET, PC-FET, and C-FET
are disabled and a Current Protection Timer is started. This timer ensures that the FETs are dis-
abled for at least one second. The application software must then set the DFE and CFE bits in
the FET Control and Status Register to re-enable normal operation. If the C-FET is re-enabled
and the charger continues to supply too high currents, the Charge Over-current Protection will
be activated again.
”Register Description for Battery Protection” on page 128
for register descriptions.
2548E–AVR–07/06