ATmega406 Atmel Corporation, ATmega406 Datasheet - Page 13
ATmega406
Manufacturer Part Number
ATmega406
Description
Manufacturer
Atmel Corporation
Specifications of ATmega406
Flash (kbytes)
40 Kbytes
Pin Count
48
Max. Operating Frequency
1 MHz
Cpu
8-bit AVR
# Of Touch Channels
8
Hardware Qtouch Acquisition
No
Max I/o Pins
18
Ext Interrupts
4
Usb Speed
No
Usb Interface
No
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
12
Adc Speed (ksps)
1.9
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-30 to 85
I/o Supply Class
4.0 to 25
Operating Voltage (vcc)
4.0 to 25
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
3
Pwm Channels
2
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATmega406-1AAU
Manufacturer:
AT
Quantity:
20 000
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5.6.1
5.7
2548E–AVR–07/06
Instruction Execution Timing
SPH and SPL – Stack Pointer Register
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
chip. No internal clock division is used.
Figure 5-4
vard architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 5-4.
Figure 5-5
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
Figure 5-5.
Bit
0x3E (0x5E)
0x3D (0x5D)
Read/Write
Initial Value
Register Operands Fetch
2nd Instruction Execute
3rd Instruction Execute
1st Instruction Execute
ALU Operation Execute
2nd Instruction Fetch
3rd Instruction Fetch
4th Instruction Fetch
1st Instruction Fetch
Total Execution Time
shows the internal timing concept for the Register File. In a single clock cycle an ALU
shows the parallel instruction fetches and instruction executions enabled by the Har-
Result Write Back
The Parallel Instruction Fetches and Instruction Executions
Single Cycle ALU Operation
SP15
R/W
R/W
SP7
15
7
0
0
clk
clk
CPU
CPU
SP14
R/W
R/W
SP6
14
6
0
0
SP13
R/W
R/W
SP5
CPU
13
5
0
0
T1
T1
, directly generated from the selected clock source for the
SP12
R/W
R/W
SP4
12
4
0
0
SP11
T2
R/W
R/W
SP3
T2
11
3
0
0
SP10
R/W
SP2
R/W
10
2
0
0
T3
T3
R/W
SP9
SP1
R/W
9
1
0
0
ATmega406
SP8
SP0
R/W
R/W
8
0
0
0
T4
T4
SPH
SPL
13
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