ATmega406 Atmel Corporation, ATmega406 Datasheet - Page 183

• Manufacturer Part Number: ATmega406
• Manufacturer: Atmel Corporation

Specifications of ATmega406

• Flash (kbytes): 40 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 1 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 18
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1.9
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -30 to 85
• I/o Supply Class: 4.0 to 25
• Operating Voltage (vcc): 4.0 to 25
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Pwm Channels: 2
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

27.5
27.5.1
2548E–AVR–07/06
Entering the Boot Loader Program
SPMCSR – Store Program Memory Control and Status Register
Entering the Boot Loader takes place by a jump or call from the application program. This may
be initiated by a trigger such as a command received via the TWI interface. Alternatively, the
Boot Reset Fuse can be programmed so that the Reset Vector is pointing to the Boot Flash start
address after a reset. In this case, the Boot Loader is started after a reset. After the application
code is loaded, the program can start executing the application code. Note that the fuses cannot
be changed by the MCU itself. This means that once the Boot Reset Fuse is programmed, the
Reset Vector will always point to the Boot Loader Reset and the fuse can only be changed
through the serial or parallel programming interface.
Table 27-4.
Note:
The Store Program Memory Control and Status Register contains the control bits needed to con-
trol the Boot Loader operations.
• Bit 7 – SPMIE: SPM Interrupt Enable
When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM
ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN
bit in the SPMCSR Register is cleared.
• Bit 6 – RWWSB: Read-While-Write Section Busy
When a Self-Programming (Page Erase or Page Write) operation to the RWW section is initi-
ated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section
cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a
Self-Programming operation is completed. Alternatively the RWWSB bit will automatically be
cleared if a page load operation is initiated.
• Bit 5 - SIGRD: Signature Row Read
If this bit is written to one at the same time as SPMEN, the next LPM instruction within three
clock cycles will read a byte from the signature row into the destination register. see “Reading
the Signature Row from Software” on page 189 for details.
An SPM instruction within four cycles after SIGRD and SPMEN are set will have no effect. This
operation is reserved for future use and should not be used.
Bit
0x37 (0x57)
Read/Write
Initial Value
BOOTRST
1
0
1. “1” means unprogrammed, “0” means programmed
SPMIE
Boot Reset Fuse
R/W
7
0
Reset Address
Reset Vector = Application Reset (address 0x0000)
Reset Vector = Boot Loader Reset (see
RWWSB
R
6
0
(1)
SIGRD
R/W
5
0
RWWSRE
R/W
4
0
BLBSET
R/W
3
0
Table 27-7 on page
PGWRT
R/W
2
0
PGERS
R/W
1
0
193)
ATmega406
SPMEN
R/W
0
0
SPMCSR
183