ATmega406 Atmel Corporation, ATmega406 Datasheet - Page 136
ATmega406
Manufacturer Part Number
ATmega406
Description
Manufacturer
Atmel Corporation
Specifications of ATmega406
Flash (kbytes)
40 Kbytes
Pin Count
48
Max. Operating Frequency
1 MHz
Cpu
8-bit AVR
# Of Touch Channels
8
Hardware Qtouch Acquisition
No
Max I/o Pins
18
Ext Interrupts
4
Usb Speed
No
Usb Interface
No
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
12
Adc Speed (ksps)
1.9
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-30 to 85
I/o Supply Class
4.0 to 25
Operating Voltage (vcc)
4.0 to 25
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
3
Pwm Channels
2
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATmega406-1AAU
Manufacturer:
AT
Quantity:
20 000
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24. Cell Balancing
136
ATmega406
ATmega406 incorporates cell balancing FETs. The chip provides one cell balancing FET for
each battery cell in series. The FETs are directly controlled by the application software, allowing
the cell balancing algorithms to be implemented in software. The FETs are connected in parallel
with the individual battery cells. The cell balancing is illustrated in
a four-cell configuration. The cell balancing FETs are disabled in the Power-off mode.
Typical current through the Cell Balancing FETs (T
controlled by the CBCR. Neighbouring FETs cannot be simultaneously enabled. If trying to
enable two neighbouring FETs, both will be disabled.
Figure 24-1. Cell Balancing
RP
RP
RP
RP
RP
T
T
T
T
CB
CB
CB
CB
PV4
PV3
PV2
PV1
NV
Level
Shift
Level
Shift
Level
Shift
Level
Shift
CB
) is 2 mA. The Cell Balancing FETs are
Control Register
Cell Balancing
Figure
24-1. The figure shows
2548E–AVR–07/06
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