ATmega406 Atmel Corporation, ATmega406 Datasheet - Page 260

• Manufacturer Part Number: ATmega406
• Manufacturer: Atmel Corporation

Specifications of ATmega406

• Flash (kbytes): 40 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 1 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 18
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1.9
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -30 to 85
• I/o Supply Class: 4.0 to 25
• Operating Voltage (vcc): 4.0 to 25
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Pwm Channels: 2
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

iv
ATmega406
22 Battery Protection ................................................................................ 125
23 FET Control .......................................................................................... 133
24 Cell Balancing ...................................................................................... 136
25 2-wire Serial Interface .......................................................................... 138
26 JTAG Interface and On-chip Debug System ..................................... 171
21.2 Writing to Bandgap Calibration Registers ...........................................................122
21.3 Register Description for Voltage Reference and Temperature Sensor ..............123
22.1 Features .............................................................................................................125
22.2 Deep Under-voltage Protection ..........................................................................126
22.3 Discharge Over-current Protection .....................................................................126
22.4 Charge Over-current Protection .........................................................................126
22.5 Short-circuit Protection .......................................................................................127
22.6 Battery Protection CPU Interface .......................................................................127
22.7 Register Description for Battery Protection ........................................................128
23.1 FET Driver ..........................................................................................................134
23.2 Register Description for FET Control ..................................................................134
24.1 Register Description ...........................................................................................137
25.1 Features .............................................................................................................138
25.2 Two-wire Serial Interface Bus Definition .............................................................138
25.3 Data Transfer and Frame Format .......................................................................139
25.4 Multi-master Bus Systems, Arbitration and Synchronization ..............................142
25.5 Overview of the TWI Module ..............................................................................144
25.6 TWI Register Description ...................................................................................147
25.7 Using the TWI .....................................................................................................150
25.8 Transmission Modes ..........................................................................................153
25.9 Multi-master Systems and Arbitration .................................................................167
25.10 Bus Connect/Disconnect for Two-wire Serial Interface ....................................169
26.1 Features .............................................................................................................171
26.2 Overview ............................................................................................................171
26.3 Test Access Port – TAP .....................................................................................171
26.4 TAP Controller ....................................................................................................173
26.5 Using the On-chip Debug System ......................................................................174
26.6 On-chip Debug Specific JTAG Instructions ........................................................175
26.7 On-chip Debug Related Register .......................................................................176
2548E–AVR–07/06