ATmega406 Atmel Corporation, ATmega406 Datasheet - Page 109

• Manufacturer Part Number: ATmega406
• Manufacturer: Atmel Corporation

Specifications of ATmega406

• Flash (kbytes): 40 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 1 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 18
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1.9
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -30 to 85
• I/o Supply Class: 4.0 to 25
• Operating Voltage (vcc): 4.0 to 25
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Pwm Channels: 2
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

18.2.1
2548E–AVR–07/06
CADCSRA – CC-ADC Control and Status Register A
charge flow estimation should be based on the self-discharge rate of the battery and the standby
current of the battery system.
• Bit 7 – CADEN: CC-ADC Enable
When the CADEN bit is cleared (zero), the CC-ADC is disabled, and any ongoing conversions
will be terminated. When the CADEN bit is set (one), the CC-ADC will continuously measure the
voltage drop over the external sense resistor R
abled. Note that the bandgap voltage reference must be enabled separately, see
Bandgap Calibration C Register” on page
• Bit 6 – Res: Reserved
This bit is reserved bit in the ATmega406 and will always read as zero.
• Bit 5 - CADUB: CC-ADC Update Busy
The CC-ADC operates in a different clock domain than the CPU. Whenever a new value is writ-
ten to CADCSRA, CADRCC or CADRDC, this value must be synchronized to the CC-ADC clock
domain. Subsequent writes to these registers will be blocked during this synchronization. Syn-
chronization of one of the registers, will block updating of all the others. The CADUB bit will be
read as one while any of these registers is being synchronized, and will be read as zero when
neither register is being synchronized.
• Bits 4:3 – CADAS1:0: CC-ADC Accumulate Current Select
The CADAS bits select the conversion time for the Accumulate Current output as shown in
18-1.
Table 18-1.
Bit
(0xE4)
Read/Write
Initial Value
CADAS1:0
00
01
10
11
CADEN
CC-ADC Accumulate Current Conversion Time
R/W
7
0
R
6
0
–
CADUB
R
5
0
CC-ADC Accumulate Current Conversion Time
CADAS1
R/W
123.
4
0
SENSE
CADAS0
R/W
3
0
. In Power-off, the CC-ADC is always dis-
125 ms
250 ms
500 ms
CADSI1
1 s
R/W
2
0
CADSI0
R/W
1
0
ATmega406
CADSE
R/W
0
0
”BGCCR –
CADCSRA
Table
109