ATmega406 Atmel Corporation, ATmega406 Datasheet - Page 100

• Manufacturer Part Number: ATmega406
• Manufacturer: Atmel Corporation

Specifications of ATmega406

• Flash (kbytes): 40 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 1 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 18
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1.9
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -30 to 85
• I/o Supply Class: 4.0 to 25
• Operating Voltage (vcc): 4.0 to 25
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Pwm Channels: 2
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

16.5.1
16.5.2
16.6
16.6.1
100
16-bit Timer/Counter Register Description
ATmega406
Compare Match Blocking by TCNT1 Write
Using the Output Compare Unit
TCCR1B – Timer/Counter1 Control Register B
Figure 16-3
bit names indicates the device number (n = 1 for Timer/Counter1), and the “x” indicates output
compare unit (A). The elements of the block diagram that are not directly a part of the output
compare unit are gray shaded.
Figure 16-3. Output Compare Unit, Block Diagram
All CPU writes to the TCNT1 Register will block any compare match that occurs in the next timer
clock cycle, even when the timer is stopped. This feature allows OCR1x to be initialized to the
same value as TCNT1 without triggering an interrupt when the Timer/Counter clock is enabled.
Since writing TCNT1 in any mode of operation will block all compare matches for one timer clock
cycle, there are risks involved when changing TCNT1 when using any of the output compare
channels, independent of whether the Timer/Counter is running or not. If the value written to
TCNT1 equals the OCR1x value, the compare match will be missed.
• Bit 7:4 – Res: Reserved Bits
These bits is a reserved bit in the ATmega406 and always reads as zero.
• Bit 3 – CTC1: Clear Timer/Counter1 on Compare Match
When the CTC1 control bit is set (one), Timer/Counter1 is reset to 0x00 in the CPU clock cycle
after a compare match.
Bit
(0x81)
Read/Write
Initial Value
shows a block diagram of the output compare unit. The small “n” in the register and
R/W
7
–
0
R/W
6
–
0
OCRnxH (8-bit)
TEMP (8-bit)
OCRnx (16-bit Register)
R
5
–
0
OCRnxL (8-bit)
DATA BUS
R/W
4
–
0
=
(16-bit Comparator )
CTC1
(8-bit)
R/W
3
0
TCNTnH (8-bit)
OCFnx (Int.Req.)
CS12
R/W
TCNTn (16-bit Counter)
2
0
CS11
R/W
TCNTnL (8-bit)
1
0
CS10
R/W
0
0
2548E–AVR–07/06
TCCR1B