AT32UC3B0512AU Atmel Corporation, AT32UC3B0512AU Datasheet - Page 60

• Manufacturer Part Number: AT32UC3B0512AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3B0512AU

• Flash (kbytes): 512 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 60 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 44
• Ext Interrupts: 44
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 4
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
60
Usage
AVR32
Cycles per instruction
Icache miss rate
Dcache read miss rate
Average instruction fetch miss latency
Fraction of execution time spent stalling due to instruction fetch misses
Average writeback stall duration
The performance counters can be used to monitor several different events and perform different
measurements. Some of the most useful are explained below.
CONF0: 0x7 (Instruction executed)
CPI = CCNT / PCNT0
Cycles-per-instruction (CPI) measures the average time it took to execute an instruction.
CONF0: 0x7 (Instruction executed)
CONF1: 0x0 (Icache miss)
ICMR = PCNT1 / PCNT0
The instruction cache miss rate (ICMR) mesures the fraction of instruction cache misses per
executed instruction.
CONF0: 0xE (Dcache read access)
CONF1: 0xA (Dcache read miss)
DCMR = PCNT1 / PCNT0
The data cache read miss rate (DCRMR) mesures the fraction of data cache read misses per
data cache read access.
CONF0: 0x1 (Instruction fetch stall)
CONF1: 0x0 (Icache miss)
AIFML = PCNT0 / PCNT1
The average instruction fetch miss latency (AIFML) mesures the average number of clock cycles
spent per instruction cache miss. This measure does not consider cycles spent due to ITLB
misses.
CONF0: 0x1 (Instruction fetch stall)
AIFML = PCNT0 / PCCNT
The fraction of execution time spent stalling due to instruction fetch misses mesures the ratio of
clock cycles spent waiting for an instruction to be fetched to the total number of execution
cycles.
CONF0: 0x8 (Write buffer full occurrences)
CONF1: 0x9 (Write buffer full cycles)
32000D–04/2011