AT32UC3B0512AU Atmel Corporation, AT32UC3B0512AU Datasheet - Page 21

• Manufacturer Part Number: AT32UC3B0512AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3B0512AU

• Flash (kbytes): 512 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 60 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 44
• Ext Interrupts: 44
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 4
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

2.11.1
32000D–04/2011
SS_STATUS - Secure State Status Register
SS_ADRF, SS_ADRR, SS_ADR0, SS_ADR1 - Secure State Address Registers
SS_SP_SYS, SS_SP_APP - Secure State SP_SYS and SP_APP Registers
SS_RAR, SS_RSR - Secure State Return Address and Return Status Registers
Configuration Registers
Register that can be used to pass status or other information from the secure state to the nonse-
cure state. Refer to
Registers used to partition memories into a secure and a nonsecure section. Refer to
“Secure state” on page 31
Read-only registers containing the SP_SYS and SP_APP values. Refer to
state” on page 31
Contains the address and status register of the sscall instruction that called secure state. Also
used when returning to nonsecure state with the retss instruction. Refer to
state” on page 31
Configuration registers are used to inform applications and operating systems about the setup
and configuration of the processor on which it is running, see
implements the following read-only configuration registers.
Figure 2-8.
Table 2-8 on page 21
Table 2-8.
CONFIG0
CONFIG1
Name
Processor ID
RESERVED
Processor revision
31
31
IMMU SZ
Processor ID
Configuration Registers
CONFIG0 Fields
26
for details.
for details.
Section 4. “Secure state” on page 31
25
Bit
31:24
23:20
19:16
shows the CONFIG0 fields.
24
DMMU SZ
23
for details.
-
Description
Specifies the type of processor. This allows the application to
distinguish between different processor implementations.
Reserved for future use.
Specifies the revision of the processor implementation.
20
20 19
19
Processor
Revision
ISET
16 15
16
15
ILSZ
AT
13 12
13
for details.
12
IASS
AR
Figure 2-8 on page
10
10 9
9
MMUT
DSET
7 6
F
6 5
Section 4. “Secure
Section 4. “Secure
5
J
DLSZ
21. The AVR32
4
P O
AVR32
3 2
3
Section 4.
S
2
DASS
D R
1
0
0
21