AT32UC3B0512AU Atmel Corporation, AT32UC3B0512AU Datasheet - Page 214

• Manufacturer Part Number: AT32UC3B0512AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3B0512AU

• Flash (kbytes): 512 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 60 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 44
• Ext Interrupts: 44
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 4
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

214
AVR32
MACWH.D – Multiply Word with Halfword and Accumulate in Doubleword
Architecture revision:
Architecture revision1 and higher.
Description
Multiplies the word and halfword register specified and adds the result to the specified double-
word-register. The halfword register is selected as either the high or low part of Ry. Only the 48
highest of the 64 possible bits in the doubleword accumulator are used. The 16 lowest bits are
cleared.
Operation:
I.
Syntax:
I.
Operands:
I.
Status Flags:
Opcode:
Example:
31
1
15
0
operand1 = Rx;
If (Ry-part == t) then operand2 = SE(Ry[31:16]) else operand2 = SE(Ry[15:0]);
(Rd+1:Rd)[63:16] ← (operand1 × operand2)[47:0] + (Rd+1:Rd)[63:16];
Rd[15:0] ← 0;
macwh.d Rd, Rx, Ry:<part>
d ∈ {0, 2, …, 14}
{x, y} ∈ {0, 1, …, 15}
part ∈ {t,b}
Q:
V:
N:
Z:
C:
macwh.dR10, R2, R3:bwill perform
(R11:R10)[63:16] ← (R2 × SE(R3[15:0])) + (R11:R10)[63:16]
R10[15:0] ← 0
1
0
29
1
0
Not affected.
Not affected.
Not affected.
Not affected.
Not affected.
12
28
0
11
1
Rx
1
25
0
8
24
0
0
7
0
1
0
0
5
0
0
4
Y
20
0
3
19
Ry
Rd
32000D–04/2011
0
16