AT32UC3B0512AU Atmel Corporation, AT32UC3B0512AU Datasheet - Page 117

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AT32UC3B0512AU

Manufacturer Part Number
AT32UC3B0512AU
Description
Manufacturer
Atmel Corporation

Specifications of AT32UC3B0512AU

Flash (kbytes)
512 Kbytes
Pin Count
64
Max. Operating Frequency
60 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
44
Ext Interrupts
44
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
4
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
96
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3B0512AU-Z2U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Table 9-10.
9.3.9.3
Table 9-11.
9.3.10
Table 9-12.
32000D–04/2011
stswp.h
stswp.w
xchg
Mnemonics
ldm
ldmts
popm
pushm
stm
stmts
Mnemonics
breakpoint
cache
csrf
csrfcz
frs
mfdr
mfsr
mtdr
mtsr
musfr
mustr
System/Control
Multiple data
Load/Store Operations (Continued)
Mutiple data
System/Control
E
E
E
E
E
C
C
E
E
C
E
C
C
C
E
E
E
E
C
C
Rp[disp], Rs
Rd, Rx, Ry
Operands / Syntax
Rp{++}, Reglist16
{, R12={-1,0,1}}
Rp{++}, Reglist16
Reglist8 {, R12={-
1,0,1}}
Reglist8
{--}Rp, Reglist16
{--}Rp, Reglist16
Operands / Syntax
Rp[disp], Op
bp
bp
frs
Rd,
DebugRegAddress
Rd, SysRegNo
DebugRegAddress,
Rs
SysRegNo, Rs
Rs
Rd
Swap bytes and store halfword with
displacement.
Swap bytes and store word with
displacement.
Exchange register and memory
Description
Load multiple registers. R12 is tested if PC
is loaded.
Load multiple registers in application
context for task switch.
Pop multiple registers from stack. R12 is
tested if PC is popped.
Push multiple registers to stack.
Store multiple registers.
Store multiple registers in application
context for task switch.
Description
Breakpoint.
Perform cache operation
Clear status register flag.
Copy status register flag to C and Z.
Invalidates the return address stack
Move debug register to Rd.
Move system register to Rd.
Move Rs to debug register.
Move Rs to system register.
Move Rs to status register
Move status register to Rd
Operation
See Instruction Set Reference
See Instruction Set Reference
SR[bp5] ← 0
C ← SR[bp5]
Z ← SR[bp5]
See Instruction Set Reference
Rd ←DebugRegister[DebugRegAddr]
Rd ← SystemRegister[SysRegNo]
DebugRegister[DebugRegAddr] ← Rs
SystemRegister[SysRegNo] ← Rs
SR[3:0] ← Rs[3:0]
Rd ← ZE(SR[3:0])
Temp ← Rs[7:0], Rs[15:8]
*(Rp+(SE(disp12) << 1) ← Temp
Temp[31:24] ← Rs[7:0],
Temp[23:16] ← Rs[15:8],
Temp[15:8] ← Rs[23:16],
Temp[7:0] ← Rs[31:24]
*(Rp+(SE(disp12) << 2) ← Temp
See Instruction Set Reference
Operation
See Instruction Set Reference
See Instruction Set Reference
See Instruction Set Reference
See Instruction Set Reference
See Instruction Set Reference
See Instruction Set Reference
AVR32
1
1
1
Rev
1
1
1
1
1
1
117
Rev
1
1
1
1
1
1
1
1
1
1
1

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