AT32UC3B0512AU Atmel Corporation, AT32UC3B0512AU Datasheet - Page 19

• Manufacturer Part Number: AT32UC3B0512AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3B0512AU

• Flash (kbytes): 512 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 60 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 44
• Ext Interrupts: 44
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 4
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32000D–04/2011
JAVA_LVx - Java Local Variable Registers
JTBA - Java Trap Base Address
JBCR - Java Write Barrier Control Register
CONFIG0 / 1 - Configuration Register 0 / 1
COUNT - Cycle Counter Register
COMPARE - Cycle Counter Compare Register
TLBEHI - MMU TLB Entry Register High Part
TLBELO - MMU TLB Entry Register Low Part
PTBR - MMU Page Table Base Register
TLBEAR - MMU TLB Exception Address Register
The Java Extension Module uses these registers to store local variables temporary.
This register contains the base address to the program code for the trapped Java instructions.
This register is used by the garbage collector in the Java Virtual Machine.
Used to describe the processor, its configuration and capabilities. The contents and functionality
of these registers is described in detail in
The COUNT register increments once every clock cycle, regardless of pipeline stalls and
flushes. The COUNT register can both be read and written. The count register can be used
together with the COMPARE register to create a timer with interrupt functionality. The COUNT
register is written to zero upon reset and compare match. Revision 3 of the AVR32 Architecture
allows some implementations to disable this automatic clearing of COUNT upon COMPARE
match, usually by programming a bit in CPUCR. Refer to the Technical Reference Manual for
the device for details. Incrementation of the COUNT register can not be disabled. The COUNT
register will increment even though a compare interrupt is pending.
The COMPARE register holds a value that the COUNT register is compared against. The COM-
PARE register can both be read and written. When the COMPARE and COUNT registers match,
a compare interrupt request is generated and COUNT is reset to 0. This interrupt request is
routed out to the interrupt controller, which may forward the request back to the processor as a
normal interrupt request at a priority level determined by the interrupt controller. Writing a value
to the COMPARE register clears any pending compare interrupt requests. The compare and
exception generation feature is disabled if the COMPARE register contains the value zero. The
COMPARE register is written to zero upon reset.
Used to interface the CPU to the TLB. The contents and functionality of the register is described
in detail in
Used to interface the CPU to the TLB. The contents and functionality of the register is described
in detail in
Contains a pointer to the start of the Page Table. The contents and functionality of the register is
described in detail in
Contains the virtual address that caused the most recent MMU error. The contents and function-
ality of the register is described in detail in
Section 5. “Memory Management Unit” on page
Section 5. “Memory Management Unit” on page
Section 5. “Memory Management Unit” on page
Section 2.11.1 “Configuration Registers” on page
Section 5. “Memory Management Unit” on page
35.
35.
35.
AVR32
35.
21.
19