AT32UC3B0512AU Atmel Corporation, AT32UC3B0512AU Datasheet - Page 35

• Manufacturer Part Number: AT32UC3B0512AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3B0512AU

• Flash (kbytes): 512 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 60 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 44
• Ext Interrupts: 44
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 4
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

5. Memory Management Unit
5.1
32000D–04/2011
Memory map in systems with MMU
The AVR32 architecture defines an optional Memory Management Unit (MMU). This allows effi-
cient implementation of virtual memory and large memory spaces. Virtual memory simplifies
execution of multiple processes and allows allocation of privileges to different sections of the
memory space.
The AVR32 architecture specifies a 32-bit virtual memory space. This virtual space is mapped
into a 32-bit physical space by a MMU. It should also be noted that not all implementations will
use caches. The cacheability information specified in the figure will therefore not apply for all
implementations. Refer to the implementation-specific Hardware Manual for details.
The virtual memory map is specified in
Figure 5-1.
The memory map has six different segments, named P0 through P4, and U0. The P-segments
are accessible in the privileged modes, while the U-segment is accessible in the unprivileged
mode.
Both the P1 and P2 segments are default segment translated to the physical address range
0x00000000 to 0x1FFFFFFF. The mapping between virtual addresses and physical addresses
is therefore implemented by clearing of MSBs in the virtual address. The difference between P1
and P2 is that P1 may be cached, depending on the cache configuration, while P2 is always
uncached. Because P1 and P2 are segment translated and not page translated, code for initial-
ization of MMUs and exception vectors are located in these segments. P1, being cacheable,
may offer higher performance than P2.
0xFFFFFFFF
0xC0000000
0xE0000000
0xA0000000
0x80000000
0x00000000
The AVR32 virtual memory space
512MB translated space,
512MB system space,
512MB non-translated
space, non-cacheable
512MB non-translated
2GB translated space
space, cacheable
Privileged Modes
non-cacheable
Cacheable
cacheable
Figure
P4
P3
P2
P1
P0
5-1.
0xFFFFFFFF
0x80000000
0x00000000
2GB translated space
Unaccessible space
Unprivileged Mode
Access error
Cacheable
AVR32
U0
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