AT32UC3B0512AU Atmel Corporation, AT32UC3B0512AU Datasheet - Page 206

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AT32UC3B0512AU

Manufacturer Part Number
AT32UC3B0512AU
Description
Manufacturer
Atmel Corporation

Specifications of AT32UC3B0512AU

Flash (kbytes)
512 Kbytes
Pin Count
64
Max. Operating Frequency
60 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
44
Ext Interrupts
44
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
4
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
96
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3B0512AU-Z2U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
206
AVR32
LSR – Logical Shift Right
Architecture revision:
Architecture revision1 and higher.
Description
Shifts all bits in a register the amount specified to the right. The shift amount may be specified by
a register or an immediate. Zeros are shifted into the MSB.
Operation:
I.
II.
III.
Syntax:
I.
II.
III.
Operands:
I.
II.
III.
Status Flags:
Rd ← LSR(Rx, Ry[4:0]);
Rd ← LSR(Rd, sa5);
Rd ← LSR(Rs, sa5);
lsr
lsr
lsr
{d, x, y} ∈ {0, 1, …, 15}
d ∈ {0, 1, …, 15}
sa ∈ {0, 1, …, 31}
{d,s} ∈ {0, 1, …, 15}
sa ∈ {0, 1, …, 31}
Format I: Shamt = Ry[4:0], Op = Rx
Format II: Shamt = sa5, Op = Rd
Format III: Shamt = sa5, Op = Rs
Q:
V:
N:
Z:
C:
Not affected
Not affected
N ← RES[31]
Z ← (RES[31:0] == 0)
if Shamt != 0
else
Rd, Rx, Ry
Rd, sa
Rd, Rs, sa
C ← Op[Shamt-1]
C ← 0
32000D–04/2011

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