AT32UC3B0512AU Atmel Corporation, AT32UC3B0512AU Datasheet - Page 59

• Manufacturer Part Number: AT32UC3B0512AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3B0512AU

• Flash (kbytes): 512 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 60 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 44
• Ext Interrupts: 44
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 4
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

7.3
Table 7-2.
32000D–04/2011
Configure field setting
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
Other
Monitorable events
Monitorable events
Event monitored and counted
Instruction cache miss. Incremented once for each instruction fetch from a cacheable memory area that did
not hit in the cache.
Instruction fetch stage stall. Incremented every cycle the memory system is unable to deliver an instruction
to the CPU.
Data hazard stall. Incremented every cycle the condition is true.
ITLB miss.
DTLB miss.
Branch instruction executed. May or may not be taken.
Branch mispredicted.
Instruction executed. Incremented once each time an instruction is completed.
Stall due to data cache write buffers full. Incremented once for each occurrence.
Stall due to data cache write buffers full. Incremented every cycle the condition is true.
Stall due to data cache read miss. Incremented once for each data access to a cacheable memory area
that did not hit in the cache.
Stall due to data cache read miss. Incremented every cycle the pipeline is stalled due to a data access to a
cacheable memory area that did not hit in the cache.
Write access counter. Incremented once for each write access.
Write access counter. Incremented every cycle a write access is ongoing.
Read access counter. Incremented once for each read access.
Read access counter. Incremented every cycle a read access is ongoing.
Cache stall counter. Incremented once for each read or write access that stalls.
Cache stall counter. Incremented every cycle a read or write access stalls. Write accesses are counted
only until the write is put in the write buffer.
Cache access counter. Incremented once for each read or write access.
Cache access counter. Incremented every cycle a read or write access is ongoing. Write accesses are
counted only until the write is put in the write buffer.
Data cache line writeback. Incremented once when a line containing dirty data is replaced in the cache.
Accumulator cache hit
Accumulator cache miss
BTB hit. Incremented once per hit occurrence.
Micro-ITLB miss. Incremented once per miss occurrence.
Micro-DTLB miss. Incremented once per miss occurrence.
Reserved.
The following events can be monitored by the performance counters, depending on the setting
of CONF0 and CONF1, see
Table 7-2 on page
59.
AVR32
59