AT32UC3B0512AU Atmel Corporation, AT32UC3B0512AU Datasheet - Page 20

• Manufacturer Part Number: AT32UC3B0512AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3B0512AU

• Flash (kbytes): 512 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 60 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 44
• Ext Interrupts: 44
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 4
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

20
MMUCR - MMU Control Register
TLBARLO / TLBARHI - MMU TLB Accessed Register Low / High
PCCNT - Performance Clock Counter
PCNT0 / PCNT1 - Performance Counter 0 / 1
PCCR - Performance Counter Control Register
BEAR - Bus Error Address Register
MPUARn - MPU Address Register n
MPUPSRn - MPU Privilege Select Register n
MPUCRA / MPUCRB - MPU Cacheable Register A / B
MPUBRA / MPUBRB - MPU Bufferable Register A / B
MPUAPRA / MPUAPRB - MPU Access Permission Register A / B
MPUCR - MPU Control Register
AVR32
Used to control the MMU and the TLB. The contents and functionality of the register is described
in detail in
Contains the Accessed bits for the TLB. The contents and functionality of the register is
described in detail in
Clock cycle counter for performance counters. The contents and functionality of the register is
described in detail in
Counts the events specified by the Performance Counter Control Register. The contents and
functionality of the register is described in detail in
57.
Controls and configures the setup of the performance counters. The contents and functionality
of the register is described in detail in
Physical address that caused a Data Bus Error. This register is Read Only. Writes are allowed,
but are ignored.
Registers that define the base address and size of the protection regions. Refer to
“Memory Protection Unit” on page 51
Registers that define which privilege register set to use for the different subregions in each pro-
tection region. Refer to
Registers that define if the different protection regions are cacheable. Refer to
ory Protection Unit” on page 51
Registers that define if the different protection regions are bufferable. Refer to
ory Protection Unit” on page 51
Registers that define the access permissions for the different protection regions. Refer to
tion 6. “Memory Protection Unit” on page 51
Register that control the operation of the MPU. Refer to
page 51
for details.
Section 5. “Memory Management Unit” on page
Section 5. “Memory Management Unit” on page
Section 7. “Performance counters” on page
Section 6. “Memory Protection Unit” on page 51
for details.
for details.
for details.
Section 7. “Performance counters” on page
for details.
Section 7. “Performance counters” on page
Section 6. “Memory Protection Unit” on
35.
57.
35.
for details.
Section 6. “Mem-
Section 6. “Mem-
57.
32000D–04/2011
Section 6.
Sec-