AT32UC3B0512AU Atmel Corporation, AT32UC3B0512AU Datasheet - Page 212

• Manufacturer Part Number: AT32UC3B0512AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3B0512AU

• Flash (kbytes): 512 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 60 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 44
• Ext Interrupts: 44
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 4
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

212
AVR32
MACSATHH.W – Multiply-Accumulate Halfwords with Saturation into Word
Architecture revision:
Architecture revision1 and higher.
Description
Multiplies the two halfword registers specified, shifts the results one position to the left and
stores the result as a temporary word-sized product. If the two operands equals -1, the product
is saturated to the largest positive 32-bit fractional number. The halfword registers are selected
as either the high or low part of the operand registers. The temporary product is added with sat-
uration to Rd.
Operation:
I.
Syntax:
I.
Operands:
I.
Status Flags:
Opcode:
Example:
31
15
0
1
If (Rx-part == t) then operand1 = SE(Rx[31:16]) else operand1 = SE(Rx[15:0]);
If (Ry-part == t) then operand2 = SE(Ry[31:16]) else operand2 = SE(Ry[15:0]);
If (operand1 == operand2 == 0x8000)
else
Rd ← Sat(product + Rd);
macsathh.w Rd, Rx:<part>, Ry:<part>
{d, x, y} ∈ {0, 1, …, 15}
part ∈ {t,b}
Q:
V:
N:
Z:
C:
macsathh.wR10, R2:t, R3:b
will perform R10 ← Sat (Sat(( SE(R2[31:16]) × SE(R3[15:0]) ) << 1) + R10)
0
1
29
0
1
product ← 0x7FFF_FFFF;
product ← (operand1 × operand2) << 1;
Set if saturation occurred, or if the accumulation overflows, or previously set.
Not affected.
Not affected.
Not affected.
Not affected.
12
28
0
11
0
Rx
1
1
25
8
0
24
0
7
1
0
6
0
0
X
5
0
Y
4
20
0
3
19
Ry
Rd
32000D–04/2011
0
16