DS3170+ Maxim Integrated Products, DS3170+ Datasheet - Page 161

• Manufacturer Part Number: DS3170+
• Description: IC TXRX DS3/E3 100-CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3170+

• Function: Single-Chip Transceiver
• Interface: DS3, E3
• Number Of Circuits: 1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 120mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LBGA
• Includes: DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 7: Receive FIFO Overflow Interrupt Enable (RFOIE) – This bit enables an interrupt if the RFOL bit is set and
the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 4: Receive Packet End Interrupt Enable (RPEIE) – This bit enables an interrupt if the RPEL bit is set and the
bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 3: Receive Packet Start Interrupt Enable (RPSIE) – This bit enables an interrupt if the RPSL bit is set and the
bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 2: Receive FIFO Full Interrupt Enable (RFFIE) – This bit enables an interrupt if the RFFL bit is set and the bit
in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 0: Receive HDLC Data Available Interrupt Enable (RHDAIE) – This bit enables an interrupt if the RHDAL bit
is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Note: The FIFO data and status are updated when the Receive FIFO Data (RFD[7:0]) is read (upper byte read).
When this register is read eight bits at a time, a read of the lower byte will reflect the status of the next read of the
upper byte, and reading the upper byte when RFDV=0 may result in a loss of data.
Bits 15 to 8: Receive FIFO Data (RFD[7:0]) – These eight bits are the packet data stored in the Receive FIFO.
RFD[7] is the MSB, and RFD[0] is the LSB. If bit reordering is disabled, RFD[0] is the first bit received, and RFD[7]
is the last bit received. If bit reordering is enabled, RFD[7] is the first bit received, and RFD[0] is the last bit
received.
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
RFOIE
RFD7
15
15
--
X
--
0
7
0
7
0
RFD6
14
14
--
--
X
--
0
6
0
6
0
HDLC.RSRIE
HDLC Receive Status Register Interrupt Enable
0B8h
HDLC.RFDR
HDLC Receive FIFO Data Register
0BCh
RFD5
13
13
--
--
X
--
0
5
0
5
0
161 of 230
RPEIE
RFD4
12
12
--
X
--
0
4
0
4
0
RPSIE
RFD3
RPS2
11
11
--
X
X
0
3
0
3
DS3170 DS3/E3 Single-Chip Transceiver
RFFIE
RFD2
RPS1
10
10
--
X
X
0
2
0
2
RFD1
RPS0
--
--
X
X
9
0
1
0
9
1
RHDAIE
RFDV
RFD0
--
X
8
0
0
0
8
0
0