DS3170+ Maxim Integrated Products, DS3170+ Datasheet - Page 159

• Manufacturer Part Number: DS3170+
• Description: IC TXRX DS3/E3 100-CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3170+

• Function: Single-Chip Transceiver
• Interface: DS3, E3
• Number Of Circuits: 1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 120mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LBGA
• Includes: DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

Bit 2: Transmit FIFO Full Interrupt Enable (TFFIE) – This bit enables an interrupt if the TFFL bit is set and the bit
in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 1: Transmit FIFO Empty Interrupt Enable (TFEIE) – This bit enables an interrupt if the TFEL bit is set and the
bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 0: Transmit HDLC Data Available Interrupt Enable (THDAIE) – This bit enables an interrupt if the THDAL bit
is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
12.6.2 HDLC Receive Side Register Map
The receive side utilizes five registers.
Table 12-17. Receive Side HDLC Register Map
12.6.2.1 Register Bit Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 12 to 8: Receive HDLC Data Available Level (RDAL[4:0]) – These five bits indicate the minimum number of
eight byte groups that must be stored (contain data) in the Receive FIFO before HDLC data is considered to be
available (RHDA=1). For example, a value of 21 (15h) results in HDLC data being available when the Receive
FIFO contains 168 (A8h) bytes or more.
Bit 3: Receive Bit Reordering Enable (RBRE) – When 0, bit reordering is disabled (The first bit received is in the
LSB of the Receive FIFO Data byte RFD[0]). When 1, bit reordering is enabled (The first bit received is in the MSB
of the Receive FIFO Data byte RFD[7]).
Bit 2: Receive Data Inversion Enable (RDIE) – When 0, the incoming data is directly passed on for packet
processing. When 1, the incoming data is inverted before being passed on for packet processing.
Bit 1: Receive FCS Processing Disable (RFPD) – When 0, FCS processing is performed (the packets have an
FCS appended). When 1, FCS processing is disabled (the packets do not have an FCS appended).
Address
0BAh
0BCh
0BEh
0B0h
0B2h
0B4h
0B6h
0B8h
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
15
HDLC.RCR
HDLC.RSR
HDLC.RSRL
HDLC.RSRIE
HDLC.RFDR
--
--
0
7
0
Register
--
--
--
14
--
--
0
6
0
HDLC Receive Control Register
Unused
HDLC Receive Status Register
HDLC Receive Status Register Latched
HDLC Receive Status Register Interrupt Enable
Unused
HDLC Receive FIFO Data Register
Unused
HDLC.RCR
HDLC Receive Control Register
0B0h
Register Description
13
--
--
0
5
0
159 of 230
RDAL4
12
--
0
4
0
RDAL3
RBRE
11
1
3
0
DS3170 DS3/E3 Single-Chip Transceiver
RDAL2
RDIE
10
0
2
0
RDAL1
RFPD
9
0
1
0
RFRST
RDAL0
8
0
0
0