DS3170+ Maxim Integrated Products, DS3170+ Datasheet - Page 142

• Manufacturer Part Number: DS3170+
• Description: IC TXRX DS3/E3 100-CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3170+

• Function: Single-Chip Transceiver
• Interface: DS3, E3
• Number Of Circuits: 1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 120mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LBGA
• Includes: DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

Bit 1: Receive Loss Of Lock Status (RLOL) This bits indicates the status of the receive LIU clock recovery PLL
circuit.
Bit 0: Performance Monitoring Update Status (PMS) This bits indicates the status of all active performance
monitoring register and counter update signals in this port. It is an “AND” of all update status bits and is not set until
all performance registers are updated and the counters reset. In software update modes, the update request bit
PORT.CR1.PMU should be held high until this status bit goes high.
Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 7: Receive Line Clock Activity Status Latched (RLCLKL) This bit will be set when the signal on the RLCLK
pin or the recovered clock from the LIU for this port is active.
Bit 6: Transmit Input Clock Activity Status Latched (TCLKIL) This bit will be set when the signal on the TCLKI
pin for this port is active.
Bit 2: Transmit Driver Monitor Status Latched (TDML) This bit will be set when the PORT.SR.TDM status bit
changes from low to high. This bit will also set the PORT.ISR.PSR status bit if the PORT.SRIE.TDMIE bit is
enabled.
corresponding GL.ISRIE.PISRIE bit is also set.
Bit 1: Receive Loss Of Lock Status Latched (RLOLL) This bit will be set when the PORT.SR.RLOL status bit
changes from low to high. This bit will also set the PORT.ISR.PSR status bit if the PORT.SRIE.RLOLIE bit is
enabled.
corresponding GL.ISRIE.PISRIE bit is also set.
Bit 0: Performance Monitoring Update Status Latched (PMSL) This bit will be set when the PORT.SR.PMS
status bit changes from low to high. This bit will also set the PORT.ISR.PSR status bit if the PORT.SRIE.PMUIE bit
is enabled. The interrupt pin will be driven when this bit is set, the PORT.SRIE.PMUIE bit is set, and the
PORT.SRIE.PMSIE bit are set.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 2: Transmit Driver Monitor Latched Status Interrupt Enable (TDMIE) The interrupt pin will be driven when
this bit is enabled and the PORT.SRL.TDML bit is set and the GL.ISRIE.PISRIE bit is enabled.
1 = Not locked to the incoming signal
0 = The associated update request signal is low
1 = The requested performance register updates are all completed
0 = Locked to the incoming signal
The interrupt pin will be driven when this bit is set, the PORT.SRIE.RLOLIE bit is set, and the
RLCLKL
The interrupt pin will be driven when this bit is set, the PORT.SRIE.TDMIE bit is set, and the
15
15
--
--
--
7
0
7
0
TCLKIL
14
14
--
--
--
6
0
6
0
PORT.SRL
Port Status Register Latched
054h
PORT.SRIE
Port Status Register Interrupt Enable
056h
13
13
--
--
--
--
5
0
5
0
142 of 230
12
12
--
--
--
--
4
0
4
0
11
11
--
--
--
--
3
0
3
0
DS3170 DS3/E3 Single-Chip Transceiver
TDMIE
TDML
10
10
--
--
2
0
2
0
RLOLIE
RLOLL
--
--
9
1
9
0
1
0
PMSIE
PMSL
--
--
8
0
8
0
0
0