DS3170+ Maxim Integrated Products, DS3170+ Datasheet - Page 146

• Manufacturer Part Number: DS3170+
• Description: IC TXRX DS3/E3 100-CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3170+

• Function: Single-Chip Transceiver
• Interface: DS3, E3
• Number Of Circuits: 1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 120mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LBGA
• Includes: DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 15 to 0: BERT Seed/Pattern (BSP[15:0]) – Lower sixteen bits of 32 bits. Register description follows next
register.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 15 to 0: BERT Seed/Pattern (BSP[31:16]) - Upper 16 bits of 32 bits.
BERT Seed/Pattern (BSP[31:0]) – These 32 bits are the programmable seed for a transmit PRBS pattern, or the
programmable pattern for a transmit or receive repetitive pattern. BSP(31) will be the first bit output on the transmit
side for a 32-bit repetitive pattern or 32-bit length PRBS. BSP(31) will be the first bit input on the receive side for a
32-bit repetitive pattern.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 5 to 3: Transmit Error Insertion Rate (TEIR[2:0]) – These three bits indicate the rate at which errors are
inserted in the output data stream. One out of every 10
of 0 disables error insertion at a specific rate. A TEIR[2:0] value of 1 result in every 10
TEIR[2:0] value of 2 result in every 100
a TEIR[2:0] value that is nonzero. If this register is written to during the middle of an error insertion process, the
new error rate will be started after the next error is inserted.
BSP15
BSP31
BSP23
BSP7
15
15
15
--
--
0
7
0
0
7
0
0
7
0
BSP14
BSP30
BSP22
BSP6
14
14
14
--
--
0
6
0
0
6
0
0
6
0
BERT.SPR1
BERT Seed/Pattern Register #1
064h
BERT.SPR2
BERT Seed/Pattern Register #2
066h
BERT.TEICR
BERT Transmit Error Insertion Control Register
068h
BSP13
BSP29
BSP21
th
TEIR2
BSP5
bit being inverted. Error insertion starts when this register is written to with
13
13
13
--
0
5
0
0
5
0
0
5
0
146 of 230
BSP12
BSP28
BSP20
TEIR1
BSP4
12
12
12
--
0
4
0
0
4
0
0
4
0
n
bits is inverted. TEIR[2:0] is the value n. A TEIR[2:0] value
BSP11
BSP27
BSP19
TEIR0
BSP3
11
11
11
--
0
3
0
0
3
0
0
3
0
DS3170 DS3/E3 Single-Chip Transceiver
BSP10
BSP26
BSP18
BSP2
BEI
10
10
10
--
0
2
0
0
2
0
0
2
0
BSP25
BSP17
BSP9
BSP1
th
TSEI
--
9
0
1
0
9
0
1
0
9
0
1
0
bit being inverted. A
MEIMS
BSP24
BSP16
BSP8
BSP0
--
8
0
0
0
8
0
0
0
8
0
0
0