DS3170+ Maxim Integrated Products, DS3170+ Datasheet - Page 137

• Manufacturer Part Number: DS3170+
• Description: IC TXRX DS3/E3 100-CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3170+

• Function: Single-Chip Transceiver
• Interface: DS3, E3
• Number Of Circuits: 1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 120mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LBGA
• Includes: DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 13: Receive Clock Output Select (RCLKS). This bit is used to select the function of the RGCLK / RCLKO
pins. See
Bit 12: Receive Start Of Frame Output Select (RSOFOS). This bit is to select the function of the RSOFO /
RDEN pins. See
Bit 10: Transmit Clock Output Select (TCLKS). This bit is used to select the function of the TGCLK / TCLKO
pins. See
Bit 9: Transmit Start Of Frame Output Select (TSOFOS). This bit is used to select the function of the TSOFO /
TDEN pins. See
Bits 7 to 6:
reference from the port sources. The 8K reference for this port can be used as the global 8K reference source. See
Table 10-13.
Table 10-13. Port 8 kHz Reference Source Table
Bit 5:
second timer.
Bit 4: LOOP Time Enable (LOOPT). When this bit is set, the port is in loop time mode. The transmit clock is set
to the receive clock from the RLCLK pin or the recovered clock from the LIU or the CLAD clock and the TCLKI pin
is not used. This function of this bit is conditional on other control bits. See
Bit 3: CLAD Transmit Clock Source Control (CLADC). This bit is used to enable the CLAD clocks as the
source of the internal transmit clock. This function of this bit is conditional on other control bits. See
more details.
PORT.CR3.P8KRS[1:0]
0 = Selects the RGCLK signal, or the drive low pin function.
1 = Selects RCLKO signal.
0 = Selects RDEN signal.
1 = Selects RSOFO signal.
0 = Selects TGCLK signal.
1 = Selects TCLKO signal.
0 = Selects TDEN signal.
1 = Selects TSOFO signal.
0 = 8 kHz reference from global source
1 = 8 kHz reference from port’s selected source
0 = Normal transmit clock operation
1 = Transmit using the receive clock
0 = Use CLAD clocks for the transmit clock as appropriate
1 = Do not use CLAD clocks for the transmit clock – (if no loopback is enabled, TCLKI is the source)
PORT 8 kHz Reference Source (P8KREF). This bit selects the source of the 8 kHz reference for one
Table
Table
P8KRS1
0X
10
11
15
Port 8 kHz Reference Source Select (P8KRS[1:0]). This bit selects the source of the 8 kHz
--
0
7
0
10-24.
10-22.
Table 10-21.
Table
10-23.
P8KRS0
14
Undefined
Internal receive framer clock
Internal transmit framer clock
--
0
6
0
PORT.CR3
Port Control Register 3
044h
P8KREF
RCLKS
13
0
5
0
SOURCE
RSOFOS
137 of 230
LOOPT
12
0
4
0
RESERVED
CLADC
11
0
3
0
DS3170 DS3/E3 Single-Chip Transceiver
Table 10-4
TCLKS
RFTS
10
0
2
0
for more details.
TSOFOS
TFTS
9
0
1
0
Table 10-4
RESERVED
TLTS
8
0
0
0
for