DS21552L+ Maxim Integrated Products, DS21552L+ Datasheet - Page 70

• Manufacturer Part Number: DS21552L+
• Description: IC TXRX T1 1-CHIP 5V 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21552L+

• Function: Single-Chip Transceiver
• Interface: E1, HDLC, J1, T1
• Number Of Circuits: 1
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: DSX-1 and CSU Line Build-Out Generator, HDLC Controller, In-Band Loop Code Generator and Detector
• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 64 Kbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 75 mA (Typ)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Ic Interface Type: Parallel, Serial
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 100
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

15.3.3.2 TRANSMIT AN HDLC MESSAGE
1) Make sure HDLC controller is done sending any previous messages and is current sending flags by checking that the
2) Enable either the THALF or TNF interrupt.
3) Read THIR to obtain TFULL status.
4) Repeat step 3.
5) Wait for interrupt, skip to step 3.
6) Disable THALF or TNF interrupt and enable TMEND interrupt.
7) Wait for an interrupt, then read TUDR status bit to make sure packet was transmitted correctly.
15.3.3.3 TRANSMIT A BOC
1) Write 6–bit code into TBOC.
2) Set SBOC bit in TBOC=1.
15.3.4 HDLC/BOC Register Description
HCR: HDLC CONTROL REGISTER (Address=00 Hex)
HSR: HDLC STATUS REGISTER (Address=01 Hex)
(MSB)
SYMBOL
SYMBOL
RBR
(MSB)
RBOC
TCRCD
TEOM
RBOC
TABT
FIFO is empty by reading the TEMPTY status bit in the TPRM register.
a) If TFULL=0, then write a byte into the FIFO and skip to next step (special case occurs when the last byte is to be
b) If TFULL=1, then skip to step 5.
TZSD
RHR
RBR
THR
TFS
written, in this case set TEOM=1 before writing the byte and then skip to step 6).
RHR
POSITION
POSITION
RPE
HCR.7
HCR.6
HCR.5
HCR.4
HCR.3
HCR.2
HCR.1
HCR.0
HSR.7
TFS
NAME AND DESCRIPTION
Receive BOC Reset. A 0 to 1 transition will reset the BOC circuitry. Must be cleared
and set again for a subsequent reset.
Receive HDLC Reset. A 0 to 1 transition will reset the HDLC controller. Must be
cleared and set again for a subsequent reset.
Transmit Flag/Idle Select.
0 = 7Eh
1 = FFh
Transmit HDLC Reset. A 0 to 1 transition will reset both the HDLC controller and the
transmit BOC circuitry. Must be cleared and set again for a subsequent reset.
Transmit Abort. A 0 to 1 transition will cause the FIFO contents to be dumped and one
FEh abort to be sent followed by 7Eh or FFh flags/idle until a new packet is initiated by
writing new data into the FIFO. Must be cleared and set again for a subsequent abort to
be sent.
Transmit End of Message. Should be set to a one just before the last data byte of a
HDLC packet is written into the transmit FIFO at TFFR. This bit will be cleared by the
HDLC controller when the last byte has been transmitted.
Transmit Zero Stuffer Defeat. Overrides internal enable.
0 = enable the zero stuffer (normal operation)
1 = disable the zero stuffer
Transmit CRC Defeat.
0 = enable CRC generation (normal operation)
1 = disable CRC generation
NAME AND DESCRIPTION
Receive BOC Detector Change of State. Set whenever the BOC detector sees a
change of state from a BOC Detected to a No Valid Code seen or vice versa. The setting
of this bit prompt the user to read the RBOC register for details.
RPS
THR
RHALF
TABT
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RNE
TEOM
THALF
TZSD
TNF
TCRCD
(LSB)
TMEND
(LSB)