DS2155 Maxim Integrated Products, DS2155 Datasheet
DS2155
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DS2155 Summary of contents
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... GENERAL DESCRIPTION The DS2155 is a software-selectable T1, E1 single-chip transceiver (SCT) for short-haul and long-haul applications. The DS2155 is composed of a line interface unit (LIU), framer, HDLC controllers, and a TDM backplane interface, and is controlled by an 8-bit parallel port configured for Intel or Motorola bus operations ...
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TABLE OF CONTENTS 1. TABLE OF CONTENTS ............................................................................................................................2 1 ........................................................................................................................................6 ABLE OF IGURES 1 ..........................................................................................................................................7 ABLE OF ABLES 2. DATA SHEET REVISION HISTORY .....................................................................................................8 3. MAIN FEATURES....................................................................................................................................10 3 UNCTIONAL ESCRIPTION 3 ...
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I/O PIN CONFIGURATION OPTIONS.................................................................................................69 13. LOOPBACK CONFIGURATION ..........................................................................................................71 13 HANNEL OOPBACK 14. ERROR COUNT REGISTERS ...............................................................................................................75 14 INE ODE IOLATION 14.1.1 T1 Operation.......................................................................................................................................76 14.1.2 E1 Operation.......................................................................................................................................76 14 ATH ODE ...
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ETHOD ARDWARE 22 ETHOD NTERNAL 22 ETHOD NTERNAL 23. HDLC CONTROLLERS ........................................................................................................................126 23 ASIC PERATION ETAILS 23.2 HDLC C ONFIGURATION 23.2.1 FIFO Control....................................................................................................................................130 23.3 HDLC M ....................................................................................................................................131 ...
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C I HANNEL NTERLEAVE 28 ..............................................................................................................................184 RAME NTERLEAVE 29. EXTENDED SYSTEM INFORMATION BUS (ESIB) .......................................................................187 30. PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER ........................................................191 31. FRACTIONAL T1/E1 SUPPORT .........................................................................................................191 32. USER-PROGRAMMABLE OUTPUT PINS........................................................................................193 33. TRANSMIT FLOW DIAGRAMS .........................................................................................................194 34. JTAG ...
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... Figure 24-11. Optional Crystal Connections ........................................................................................................... 162 Figure 26-1. Simplified Diagram of BERT in Network Direction .......................................................................... 171 Figure 26-2. Simplified Diagram of BERT in Backplane Direction ....................................................................... 171 Figure 28-1. IBO Example ...................................................................................................................................... 186 Figure 29-1. ESIB Group of Four DS2155s ............................................................................................................ 187 Figure 33-1. T1 Transmit Flow Diagram ................................................................................................................ 194 Figure 33-2. E1 Transmit Flow Diagram ................................................................................................................ 195 Figure 34-1. JTAG Functional Block Diagram ....................................................................................................... 199 Figure 34-2 ...
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Figure 35-23. Transmit IBO Frame Interleave Mode Timing ................................................................................. 221 Figure 37-1. Intel Multiplexed Bus Read Timing (BTS = 0/MUX = 1).................................................................. 225 Figure 37-2. Intel Multiplexed Bus Write Timing (BTS = 0/MUX = 1)................................................................. 225 Figure 37-3. Motorola Multiplexed ...
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... Added lead-free packages to Ordering Information table on page 1. 100903 Add revision history table: The previous version of the DS2155 data sheet (12-06-02) did not incorporate a revision history table and did not describe new features added to B1 revision of the DS2155. THE FOLLOWING WERE INADVERTENTLY REMOVED FROM THE ...
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... Add note for FASRC bit. Add T1 and E1 Transmit Flow Chart. Added RCLK to BPCLK timing diagram. THE FOLLOWING ARE NEW FEATURES AVAILABLE ON THE DS2155 REV B1 AND ARE EXPLAINED IN THE BODY OF THE DATA SHEET Add FRAS0, TCCS, RCCS and GRSRE bits to Signaling Control Register (SIGCR) ...
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... MAIN FEATURES The DS2155 contains all of the features of the previous generation of Dallas Semiconductor’s T1 and E1 SCTs plus many new features. General Programmable output clocks for fractional T1, E1, H0, and H12 applications Interleaving PCM bus operation 8-bit parallel control port, multiplexed or nonmultiplexed, Intel or Motorola IEEE 1149 ...
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Flexible signaling support – Software or hardware based – Interrupt generated on change of signaling data – Receive signaling freeze on loss-of-sync, carrier loss, or frame slip Addition of hardware pins to indicate carrier loss and signaling freeze Automatic RAI ...
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... The DS2155 is compliant with the following standards: ANSI: T1.403-1995, T1.231–1993, T1.408 AT&T: TR54016, TR62411 ITU: G.703, G.704, G.706, G.736, G.775, G.823, G.932, I.431, O.151, Q.161 ITU-T: Recommendation I.432–03/93 B-ISDN User-Network Interface—Physical Layer Specification ETSI: ETS 300 011, ETS 300 166, ETS 300 233, CTR12, CTR4 Japanese: JTG ...
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... Functional Description The DS2155 is a software-selectable T1, E1 single-chip transceiver (SCT) for short-haul and long- haul applications. The DS2155 is composed of an LIU, framer, HDLC controllers, and a TDM backplane interface, and is controlled by an 8-bit parallel port configured for Intel or Motorola bus operations. The DS2155 is pin and software compatible with the DS2156 ...
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Reader’s Note: This data sheet assumes a particular nomenclature of the T1 operating environment. In each 125µs frame there are 24 8-bit channels plus a framing bit assumed that the framing bit is sent first followed by channel ...
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... Block Diagram Figure 3-1 shows a simplified block diagram featuring the major components of the DS2155. Details are shown in subsequent figures. The block diagram is divided into three functional blocks: LIU, FRAMER, and BACKPLANE INTERFACE. Figure 3-1. Block Diagram CLOCK EXTERNAL ACCESS CLOCK TO RECEIVE SIGNALS ADAPTER ...
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Figure 3-2. Receive and Transmit LIU 32.768MHz RRING RTIP TRING TTIP VCO / PLL MUX 16 of 238 RCL MUX JACLK RPOS RNEG RCLK TPOS TNEG TCLK ...
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Figure 3-3. Receive and Transmit Framer/HDLC RPOS RNEG RCLK TPOS TNEG TCLK REC HDLC #1 128 Byte FIFO MAPPER DATA RECEIVE CLOCK FRAMER SYNC SYNC TRANSMIT CLOCK FRAMER DATA MAPPER XMIT HDLC #1 128 Byte FIFO 17 of 238 REC ...
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Figure 3-4. Backplane Interface DATA CLOCK SYNC SYNC Sa/FDL DATA INSERT CLOCK JACLK Sa BIT/FDL EXTRACTION SIGNALING BUFFER ELASTIC STORE CHANNEL TIMING SIGNALING BUFFER ELASTIC STORE CHANNEL TIMING TCLK MUX 18 of 238 RLINK RLCLK RSIG RSIGFR RSYSCLK RSER RCLK ...
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PIN FUNCTION DESCRIPTION 4.1 Transmit Side Signal Name: TCLK Signal Description: Transmit Clock Signal Type: Input A 1.544MHz (T1 2.048MHz (E1) primary clock. Used to clock data through the transmit-side formatter. TCLK can be internally sourced from ...
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Signal Name: TLINK Signal Description: Transmit Link Data Signal Type: Input If enabled, this pin is sampled on the falling edge of TCLK for data insertion into either the FDL stream (ESF) or the Fs-bit position (D4), or the Z-bit ...
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Signal Description: Transmit Clock Output Signal Type: Output Buffered clock that is used to clock data through the transmit-side formatter (i.e., either TCLK or RCLKI). This pin is normally connected to TCLKI. Signal Name: TPOSI Signal Description: Transmit Positive-Data Input ...
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Signal Name: RCHBLK Signal Description: Receive Channel Block Signal Type: Output A user-programmable output that can be forced high or low during any of the channels. Synchronous with RCLK when the receive-side elastic store is ...
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Signal Name: RLOS/LOTC Signal Description: Receive Loss-of-Sync/Loss-of-Transmit Clock Signal Type: Output A dual function output that is controlled by the CCR1.0 control bit. This pin can be programmed to either toggle high when the synchronizer is searching for the frame ...
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... Signal Type: Input A dual function pin. A 0-to-1 transition issues a hardware reset to the DS2155 register set. A reset clears all configuration registers. Configuration register contents are set to 0. Leaving TSTRST high tri-states all output and I/O pins (including the parallel control port). Set low for normal operation. Useful in board-level testing. ...
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... Used to group two to eight DS2155s into a bus-sharing mode for alarm and status reporting. See Section more details. Signal Name: ESIBRD Signal Description: Extended System Information Bus Read Signal Type: Input/Output Used to group two to eight DS2155s into a bus-sharing mode for alarm and status reporting. See Section more details 238 29 for 29 for 29 ...
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User Output Port Pins Signal Name: UOP0 Signal Description: User Output Port 0 Signal Type: Output This output port pin can be set low or high by the CCR4.0 control bit. This pin is forced low on power-up and ...
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JTAG Test Access Port Pins Signal Name: JTRST Signal Description: IEEE 1149.1 Test Reset Signal Type: Input JTRST is used to asynchronously reset the test access port controller. After power-up, JTRST must be toggled from low to high. This ...
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... T1 and E1 modes. A quartz crystal of 2.048MHz can be applied across MCLK and XTALD instead of the clock source. The clock rate can be 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz. When using the DS2155 in T1-only operation, a 1.544MHz (50ppm) clock source can be used. Signal Name: XTALD ...
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Supply Pins Signal Name: DVDD Signal Description: Digital Positive Supply Signal Type: Supply 3.3V ±5%. Should be connected to the RVDD and TVDD pins. Signal Name: RVDD Signal Description: Receive Analog Positive Supply Signal Type: Supply 3.3V ±5%. Should ...
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... L and G Package Pinout The DS2155 is available in either a 100-pin LQFP (L) or 10mm CSBGA, 0.8mm pitch (G) package. Table 4-A. Pin Description Sorted by Pin Number PIN LQFP CSBGA ...
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PIN LQFP CSBGA 51 K10 J10 H10 F10 E10 D10 ...
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CSBGA Pin Configuration Figure 4-1. 10mm CSBGA Pin Configuration RLOS/ RCHBLK RFSYNC LOTC B JTCLK JTMS RSYSCLK C JTDI RCL BPCLK D JTDO UOP1 UOP0 E 8XCLK LIUC BTS F RTIP RRING RVDD G ...
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... R/W Interrupt Mask Register 5 20 R/W Status Register 6 21 R/W Interrupt Mask Register 6 22 R/W Status Register 7 23 R/W Interrupt Mask Register 7 24 R/W Status Register 8 37 for more details. REGISTER NAME 33 of 238 DS2155 SYMBOL PAGE MSTRREG 40 IOCR1 69 IOCR2 70 T1RCR1 46 T1RCR2 47 T1TCR1 48 T1TCR2 49 T1CCR1 50 SSIE1 93 SSIE2 ...
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... Per-Channel Loopback Enable Register 4 4F R/W Elastic Store Control Register 50 R/W Transmit Signaling Register 1 51 R/W Transmit Signaling Register 2 52 R/W Transmit Signaling Register 3 53 R/W Transmit Signaling Register 4 REGISTER NAME 34 of 238 DS2155 SYMBOL PAGE IMR8 112 SR9 174 IMR9 175 PCPR 43 PCDR1 44 PCDR2 44 PCDR3 44 PCDR4 ...
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... W Idle Array Address Register 7F R/W Per-Channel Idle Code Value Register 80 R/W Transmit Idle Code Enable Register 1 81 R/W Transmit Idle Code Enable Register 2 82 R/W Transmit Idle Code Enable Register 3 REGISTER NAME 35 of 238 DS2155 SYMBOL PAGE TS5 91 TS6 91 TS7 91 TS8 91 TS9 91 TS10 91 TS11 91 ...
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... AE R HDLC #2 Receive FIFO AF R HDLC #2 Transmit FIFO Buffer Available B0 R/W Extend System Information Bus Control Register 1 B1 R/W Extend System Information Bus Control Register 2 REGISTER NAME 36 of 238 DS2155 SYMBOL PAGE TCICE4 99 RCICE1 100 RCICE2 100 RCICE3 100 RCICE4 100 RCBR1 101 ...
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... BERT Repetitive Pattern Set Register 1 DD R/W BERT Repetitive Pattern Set Register 2 DE R/W BERT Repetitive Pattern Set Register 3 DF R/W BERT Repetitive Pattern Set Register 4 E0 R/W BERT Control Register 1 REGISTER NAME 37 of 238 DS2155 SYMBOL PAGE ESIB1 190 ESIB2 190 ESIB3 190 ESIB4 190 IBCC 164 TCD1 165 ...
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... Number-of-Errors Left — Test Register * F1–F9 — Test Register * FA–FF — Test Register *TEST1 to TEST16 registers are used only by the factory. REGISTER NAME 38 of 238 DS2155 SYMBOL PAGE BC2 173 — — BBC1 177 BBC2 177 BBC3 177 BBC4 177 BEC1 ...
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... PROGRAMMING MODEL The DS2155 register map is divided into three groups: T1 specific features, E1 specific features, and common features. The typical programming sequence begins with issuing a reset to the DS2155, selecting operation in the master mode register, enabling functions and enabling the common functions ...
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... T1 operation operation Bits 2, 3/Test Mode Bits (TEST0, TEST1). Test modes are used to force the output pins of the DS2155 into known states. This can facilitate the checkout of assemblies during the manufacturing process and also be used to isolate devices from shared buses. ...
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... The user always proceeds a read of any of the status registers with a write. The byte written to the register informs the DS2155 which bits the user wishes to read and have cleared. The user writes a byte to one of these registers, with the bit positions the user wishes to read and the bit positions the user does not wish to obtain the latest information on ...
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Information Registers Information registers operate the same as status registers except they cannot cause interrupts. They are all latched except for INFO7 and some of the bits in INFO5 and INFO6. INFO7 register is a read-only register. It reports ...
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SPECIAL PER-CHANNEL REGISTER OPERATION Some of the features described in the data sheet that operate on a per-channel basis use a special method for channel selection. There are five registers involved: per-channel pointer register (PCPR) and per- channel data ...
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Register Name: PCDR1 Register Description: Per-Channel Data Register 1 Register Address: 29h Bit # 7 6 Name — — Default CH8 CH7 Register Name: PCDR2 Register Description: Per-Channel Data Register 2 Register Address: 2Ah Bit # 7 6 Name — ...
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... CLOCK MAP Figure 8-1 shows the clock map of the DS2155. The routing for the transmit and receive clocks are shown for the various loopback modes and jitter attenuator positions. Although there is only one jitter attenuator, which can be placed in the receive or transmit path, two are shown for simplification and clarity. ...
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... T1 FRAMER/FORMATTER CONTROL AND STATUS REGISTERS The T1 framer portion of the DS2155 is configured through a set of nine control registers. Typically, the control registers are only accessed when the system is first powered up. Once the DS2155 has been initialized, the control registers only need to be accessed when there is a change in the system configuration ...
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Register Name: T1RCR2 Register Description: T1 Receive Control Register 2 Register Address: 04h Bit # 7 6 Name — RFM Default 0 0 Bit 0/Receive-Side D4 Yellow Alarm Select (RD4YM bit 2 of all channels 1 ...
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Register Name: T1TCR1 Register Description: T1 Transmit Control Register 1 Register Address: 05h Bit # 7 6 Name TJC TFPT Default 0 0 Bit 0/Transmit Yellow Alarm (TYEL not transmit yellow alarm 1 = transmit yellow alarm ...
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Register Name: T1TCR2 Register Description: T1 Transmit Control Register 2 Register Address: 06h Bit # 7 6 Name TB8ZS TSLC96 Default 0 0 Bit 0/Transmit-Side Bit 7 Zero-Suppression Enable (TB7ZS stuffing occurs 1 = bit 7 forced ...
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... through 23. Violations for the transmit and receive data streams are reported in the INFO1.6 and INFO1.7 bits, respectively. When this bit is set to 1, the DS2155 forces the transmitted stream to meet this requirement no matter the content of the transmitted stream. When running B8ZS, this bit should be set to 0 since B8ZS encoded data streams cannot violate the pulse density requirements ...
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... ESF Yellow Alarm (an unscheduled message). Setting the RAIS-CI bit in the T1CCR1 register causes the DS2155 to transmit the RAI-CI code. The RAI-CI code causes a standard Yellow Alarm to be detected by the receiver. When the host processor detects a Yellow Alarm, it can then test the alarm for the RAI-CI state by checking the BOC detector for the RAI-CI flag ...
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T1 Receive-Side Digital-Milliwatt Code Generation Receive-side digital-milliwatt code generation involves using the receive digital-milliwatt registers (T1RDMR1/2/3) to determine which of the 24 T1 channels of the T1 line going to the backplane should be overwritten with a digital-milliwatt pattern. ...
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Register Name: INFO1 Register Description: Information Register 1 Register Address: 10h Bit # 7 6 Name RPDV TPDV Default 0 0 Bit 0/Frame Bit-Error Event (FBE). Set when an Ft (D4) or FPS (ESF) framing bit is received in error. ...
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... Note 1: The definition of Blue Alarm (or AIS unframed all-ones signal. Blue Alarm detectors should be able to operate properly in the presence of a 10E-3 error rate and they should not falsely trigger on a framed all-1s signal. Blue Alarm criteria in the DS2155 has been set to achieve this performance recommended that the RBL bit be qualified with the RLOS bit. ...
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... E1 FRAMER/FORMATTER CONTROL AND STATUS REGISTERS The E1 framer portion of the DS2155 is configured by a set of four control registers. Typically, the control registers are only accessed when the system is first powered up. Once the DS2155 has been initialized, the control registers need only to be accessed when there is a change in the system configuration ...
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... CRC4 codewords out of 1000 received in error Two consecutive MF alignment words received in error Sa6S Sa5S Sa4S for details. 35 for details. 35 for details. 35 for details. 35 for details 238 ITU SPEC. G.706 4.1.1 4.1.2 G.706 4.2 and 4.3.2 G.732 5 — — RCLA DS2155 ...
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Register Name: E1TCR1 Register Description: E1 Transmit Control Register 1 Register Address: 35h Bit # 7 6 Name TFPT T16S Default 0 0 Bit 0/Transmit CRC4 Enable (TCRC4 CRC4 disabled 1 = CRC4 enabled Bit 1/Transmit G.802 Enable ...
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Register Name: E1TCR2 Register Description: E1 Transmit Control Register 2 Register Address: 36h Bit # 7 6 Name Sa8S Sa7S Default 0 0 Bit 0/Automatic Remote Alarm Generation (ARA disabled 1 = enabled Bit 1/Automatic AIS Generation (AAIS) ...
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... FAS synchronization (if CRC4 is enabled). If any one or more of these conditions is present, then the framer transmits an RAI alarm. RAI generation conforms to ETS 300 011 specifications and a constant remote alarm is transmitted if the DS2155 cannot find CRC4 multiframe synchronization within 400ms as per G.706. ...
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E1 Information Registers Register Name: INFO3 Register Description: Information Register 3 Register Address: 12h Bit # 7 6 Name — — Default 0 0 Bit 0/CAS Resync Criteria Met Event (CASRC). Set when two consecutive CAS MF alignment words ...
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Table 10-B. E1 Alarm Criteria ALARM SET CRITERIA An RLOS condition exists on power-up prior to initial synchronization, when a RLOS resync criteria has been met, or when a manual resync has been initiated by E1RCR1.0 RCL 255 or 2048 ...
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COMMON CONTROL AND STATUS REGISTERS Register Name: CCR1 Register Description: Common Control Register 1 Register Address: 70h Bit # 7 6 Name MCLKS CRC4R Default 0 0 Bit 0/Function of the RLOS/LOTC Output (RLOSF receive loss of ...
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... Bits 0 to 3/Chip Revision Bits (ID0 to ID3). The lower four bits of the IDR are used to display the die revision of the chip. IDO is the LSB of a decimal code that represents the chip revision. Bits 4 to 7/Device ID (ID4 to ID7). The upper four bits of the IDR are used to display the DS2155 ID. 11.1 T1/E1 Status Registers ...
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Register Name: IMR2 Register Description: Interrupt Mask Register 2 Register Address: 19h Bit # 7 6 Name RYELC RUA1C Default 0 0 Bit 0/Receive Loss-of-Sync Condition (RLOS interrupt masked 1 = interrupt enabled—interrupts on rising edge only Bit ...
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Register Name: SR3 Register Description: Status Register 3 Register Address: 1Ah Bit # 7 6 Name LSPARE LDN Default 0 0 Bit 0/Receive Remote Alarm Condition (RRA) (E1 Only). Set when a remote alarm is received at RPOSI and RNEGI. ...
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Register Name: IMR3 Register Description: Interrupt Mask Register 3 Register Address: 1Bh Bit # 7 6 Name LSPARE LDN Default 0 0 Bit 0/Receive Remote Alarm Condition (RRA interrupt masked 1 = interrupt enabled—interrupts on rising and falling ...
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Register Name: SR4 Register Description: Status Register 4 Register Address: 1Ch Bit # 7 6 Name RAIS-CI RSAO Default 0 0 Bit 0/Receive Align Frame Event (RAF) (E1 Only). Set every 250µs at the beginning of align frames. Used to ...
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Register Name: IMR4 Register Description: Interrupt Mask Register 4 Register Address: 1Dh Bit # 7 6 Name RAIS-CI RSAO Default 0 0 Bit 0/Receive Align Frame Event (RAF interrupt masked 1 = interrupt enabled Bit 1/Receive CRC4 Multiframe ...
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I/O PIN CONFIGURATION OPTIONS Register Name: IOCR1 Register Description: I/O Configuration Register 1 Register Address: 01h Bit # 7 6 Name RSMS RSMS2 Default 0 0 Bit 0/Output Data Format (ODF bipolar data at TPOSO and TNEGO ...
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Register Name: IOCR2 Register Description: I/O Configuration Register 2 Register Address: 02h Bit # 7 6 Name RCLKINV TCLKINV Default 0 0 Bit 0/RSYSCLK Mode Select (RSCLKM RSYSCLK is 1.544MHz RSYSCLK is 2.048MHz or ...
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... Bit 0/Framer Loopback (FLB). This loopback is useful in testing and debugging applications. In FLB, the DS2155 loops data from the transmit side back to the receive side. When FLB is enabled, the following occurs Mode: An unframed all-ones code is transmitted at TPOSO and TNEGO. E1 Mode: Normal data is transmitted at TPOSO and TNEGO. ...
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Bit 3/Local Loopback (LLB). In this loopback, data continues to be transmitted as normal through the transmit side of the SCT. Data being received at RTIP and RRING are replaced with the data being transmitted. Data in this loopback passes ...
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Per-Channel Loopback The per-channel loopback registers (PCLRs) determine which channels (if any) from the backplane should be replaced with the data from the receive side or, i.e., off of the line. If this loopback is enabled, ...
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Register Name: PCLR3 Register Description: Per-Channel Loopback Enable Register 3 Register Address: 4Dh Bit # 7 6 Name CH24 CH23 Default 0 0 Bits 0 to 7/Per-Channel Loopback Enable for Channels (CH17 to CH24 loopback ...
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... ERROR COUNT REGISTERS The DS2155 contains four counters that are used to accumulate line-coding errors, path errors, and synchronization errors. Counter update options include one-second boundaries, 42ms (T1 mode only), 62ms (E1 mode only), or manual. See Error-Counter Configuration Register (ERCNT). When updated automatically, the user can use the interrupt from the timer to determine when to read these registers. All four counters saturate at their respective maximum counts, and they do not roll over ...
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Line-Code Violation Count Register (LCVCR) 14.1.1 T1 Operation T1 code violations are defined as bipolar violations (BPVs) or excessive 0s. If the B8ZS mode is set for the receive side, then B8ZS codewords are not counted. This counter is ...
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Register Name: LCVCR1 Register Description: Line-Code Violation Count Register 1 Register Address: 42h Bit # 7 6 Name LCVC15 LCVC14 Default 0 0 Bits 0 to 7/Line-Code Violation Counter Bits (LCVC8 to LCVC15). LCV15 is the MSB ...
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... COUNTED IN THE PCVCRs No Errors in the Ft pattern Yes Errors in both the Ft and Fs patterns Errors in the CRC6 codewords PCVC13 PCVC12 PCVC11 PCVC5 PCVC4 PCVC3 238 2 1 PCVC10 PCVC9 PCVC8 PCVC2 PCVC1 PCVC0 DS2155 0 0 ...
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Frames Out-of-Sync Count Register (FOSCR) 14.3.1 T1 Operation The FOSCR is used to count the number of multiframes that the receive synchronizer is out of sync. This number is useful in ESF applications needing to measure the parameters loss-of-frame ...
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E-Bit Counter (EBCR) This counter is only available in E1 mode. E-bit count register 1 (EBCR1) is the most significant word and EBCR2 is the least significant word of a 16-bit counter that records far-end block errors (FEBE) as ...
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... DS0 MONITORING FUNCTION The DS2155 has the ability to monitor one DS0 64kbps channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction, the user determines which channel monitored by properly setting the TCM0 to TCM4 bits in the TDS0SEL register. In the receive direction, the RCM0 to RCM4 bits in the RDS0SEL register need to be properly set ...
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Register Name: RDS0SEL Register Description: Receive Channel Monitor Select Register Address: 76h Bit # 7 6 Name — — Default 0 0 Bits 0 to 4/Receive Channel Monitor Bits (RCM0 to RCM4). RCM0 is the LSB of a 5-bit channel ...
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... Change-of-State To avoid constant monitoring of the receive signaling registers, the DS2155 can be programmed to alert the host when any specific channel or channels undergo a change of their signaling state. RSCSE1–RSCSE4 for E1 and RSCSE1–RSCSE3 for T1 are used to select which channels can cause a change-of-state indication ...
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Hardware-Based Receive Signaling In hardware-based signaling the signaling data can be obtained from the RSER pin or the RSIG pin. RSIG is a signaling PCM stream output on a channel-by-channel basis from the signaling buffer. The signaling data, T1 ...
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Register Name: SIGCR Register Description: Signaling Control Register Register Address: 40h Bit # 7 6 Name GRSRE — Default 0 0 Bit 0/Force Receive Signaling All Ones (FRSAO mode, this bit forces all signaling data at the RSIG ...
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... CH23-C CH23-D RS12 (LSB) CH1-A CH1-B RS1 CH3-A CH3-B RS2 CH5-A CH5-B RS3 CH7-A CH7-B RS4 RS5 CH9-A CH9-B CH11-A CH11-B RS6 CH13-A CH13-B RS7 CH15-A CH15-B RS8 CH17-A CH17-B RS9 CH19-A CH19-B RS10 CH21-A CH21-B RS11 CH23-A CH23-B RS12 DS2155 ...
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... CH29-C CH29-D RS16 (LSB RS1 15 16 RS2 23 24 RS3 31 32 RS4 39 40 RS5 47 48 RS6 55 56 RS7 63 64 RS8 71 72 RS9 79 80 RS10 87 88 RS11 95 96 RS12 103 104 RS13 111 112 RS14 119 120 RS15 127 128 RS16 DS2155 ...
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... CH5 CH4 CH3 CH13 CH12 CH11 CH21 CH20 CH19 CH29 CH28 CH27 88 of 238 (LSB) CH2 CH1 RSCSE1 CH10 CH9 RSCSE2 CH18 CH17 RSCSE3 CH26 CH25 RSCSE4 (LSB) CH2 CH1 RSINFO1 CH10 CH9 RSINFO2 CH18 CH17 RSINFO3 CH26 CH25 RSINFO4 DS2155 ...
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Transmit Signaling Figure 16-2. Simplified Diagram of Transmit Signaling Path T1/E1 DATA STREAM ONLY APPLIES TO T1 MODE 16.2.1 Processor-Based Mode In processor-based mode, signaling data is loaded into the transmit signaling registers (TS1–TS16) by the host interface. On ...
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E1 Mode In E1 mode, TS16 carries the signaling information. This information can be in either CCS (common channel signaling) or CAS (channel associated signaling) format. The 32 time slots are referenced by two different channel number schemes in ...
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... CH29-C CH29-D TS16 (LSB TS1 15 16 TS2 23 24 TS3 31 32 TS4 39 40 TS5 47 48 TS6 55 56 TS7 63 64 TS8 71 72 TS9 79 80 TS10 87 88 TS11 95 96 TS12 103 104 TS13 111 112 TS14 119 120 TS15 127 128 TS16 DS2155 ...
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... CH23-C CH23-D TS12 (LSB) TS1 CH1-A CH1-B CH3-A CH3-B TS2 TS3 CH5-A CH5-B CH7-A CH7-B TS4 CH9-A CH9-B TS5 CH11-A CH11-B TS6 CH13-A CH13-B TS7 CH15-A CH15-B TS8 CH17-A CH17-B TS9 CH19-A CH19-B TS10 CH21-A CH21-B TS11 CH23-A CH23-B TS12 DS2155 ...
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Software Signaling Insertion-Enable Registers, E1 CAS Mode In E1 CAS mode, the CAS signaling alignment/alarm byte can be sourced from the transmit signaling registers along with the signaling data. Register Name: SSIE1 Register Description: Software Signaling Insertion Enable 1 ...
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Register Name: SSIE3 Register Description: Software Signaling Insertion Enable 3 Register Address: 0Ah Bit # 7 6 Name CH22 CH21 Default 0 0 Bit 0/Lower CAS Align/Alarm Word (LCAW). Selects the lower CAS align/alarm bits (xyxx sourced from ...
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Software Signaling Insertion-Enable Registers, T1 Mode In T1 mode, only registers SSIE1–SSIE3 are used since there are only 24 channels frame. Register Name: SSIE1 Register Description: Software Signaling Insertion Enable 1 Register Address: 08h Bit # ...
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... When operated in the T1 mode, only the first 24 channels are used by the DS2155, the remaining channels, CH25–CH32, are not used. The DS2155 contains a 64-byte idle code array accessed by the idle array address register (IAAR) and the per-channel idle code register (PCICR). The contents of the array contain the idle codes to be substituted into the appropriate transmit or receive channels. This substitution can be enabled and disabled on a per- channel basis by the transmit-channel idle code-enable registers (TCICE1– ...
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Idle-Code Programming Examples Example 1 Sets transmit channel 3 idle code to 7Eh. Write IAAR = 02h ;select channel 3 in the array Write PCICR = 7Eh ;set idle code to 7Eh Example 2 Sets transmit channels 3, 4, ...
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Register Name: IAAR Register Description: Idle Array Address Register Register Address: 7Eh Bit # 7 6 Name GRIC GTIC Default 0 0 Bits 0 to 5/Channel Pointer Address Bits (IAA0 to IAA5). These bits select the channel to be programmed ...
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The transmit-channel idle-code enable registers (TCICE1/2/3/4) are used to determine which of the channels from the backplane to the line should be overwritten with the code placed in the per-channel code array. ...
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The receive-channel idle-code enable registers (RCICE1/2/3/4) are used to determine which of the channels from the backplane to the line should be overwritten with the code placed in the per-channel code array. ...
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... These outputs can be used to block clocks to a USART or LAPD controller in ISDN-PRI applications. When the appropriate bits are set the RCHBLK and TCHBLK pins are held high during the entire corresponding channel time. Channels 25 through 32 are ignored when the DS2155 is operated in the T1 mode. Register Name: RCBR1 ...
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Register Name: RCBR3 Register Description: Receive Channel Blocking Register 3 Register Address: 8Ah Bit # 7 6 Name CH24 CH23 Default 0 0 Bits 0 to 7/Receive Channels Channel Blocking Control Bits (CH17 to CH24 ...
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Register Name: TCBR1 Register Description: Transmit Channel Blocking Register 1 Register Address: 8Ch Bit # 7 6 Name CH8 CH7 Default 0 0 Bits 0 to 7/Transmit Channels Channel Blocking Control Bits (CH1 to CH8 ...
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... The elastic stores have two main purposes. Firstly, they can be used for rate conversion. When the DS2155 is in the T1 mode, the elastic stores can rate-convert the T1 data stream to a 2.048MHz backplane mode, the elastic store can rate-convert the E1 data stream to a 1.544MHz backplane. ...
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Register Name: ESCR Register Description: Elastic Store Control Register Register Address: 4Fh Bit # 7 6 Name TESALGN TESR Default 0 0 Bit 0/Receive Elastic Store Enable (RESE elastic store is bypassed 1 = elastic store is enabled ...
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Register Name: SR5 Register Description: Status Register 5 Register Address: 1Eh Bit # 7 6 Name — — Default 0 0 Bit 0/Receive Elastic Store Slip-Occurrence Event (RSLIP). Set when the receive elastic store has either repeated or deleted a ...
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Receive Side See the IOCR1 and IOCR2 registers for information about clock and I/O configurations. If the receive-side elastic store is enabled, then the user must provide either a 1.544MHz or 2.048MHz clock at the RSYSCLK pin. For higher ...
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T1 Mode If the user selects to apply a 2.048MHz clock to the TSYSCLK pin, then the data input at TSER is ignored every fourth channel. Therefore channels 13, 17, 21, 25, and 29 (time slots ...
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... G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY) The DS2155 can implement the G.706 CRC-4 recalculation at intermediate path points. When this mode is enabled, the data stream presented at TSER already has the FAS/NFAS, CRC multiframe alignment word, and CRC-4 checksum in time slot 0. The user can modify the Sa bit positions. This change in data content is used to modify the CRC-4 checksum ...
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... T1 BIT-ORIENTED CODE (BOC) CONTROLLER The DS2155 contains a BOC generator on the transmit side and a BOC detector on the receive side. The BOC function is available only in T1 mode. 21.1 Transmit BOC Bits the TFDL register contain the BOC message to be transmitted. Setting BOCC causes the transmit BOC controller to immediately begin inserting the BOC sequence into the FDL bit position ...
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Register Name: BOCC Register Description: BOC Control Register Register Address: 37h Bit # 7 6 Name — — Default 0 0 Bit 0/Send BOC (SBOC). Set = 1 to transmit the BOC code placed in bits ...
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Register Name: SR8 Register Description: Status Register 8 Register Address: 24h Bit # 7 6 Name — — Default 0 0 Bit 0/Receive BOC Detector Change-of-State Event (RBOC). Set whenever the BOC detector sees a change of state to a ...
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... ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION (E1 ONLY) When operated in the E1 mode, the DS2155 provides three methods for accessing the Sa and the Si bits. The first method involves a hardware scheme that uses the RLINK/RLCLK and TLINK/TLCLK pins (Section 22.1). The second method involves using the internal RAF/RNAF and TAF/TNAF registers (Section 22 ...
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Register Name: RAF Register Description: Receive Align Frame Register Register Address: C6h Bit # 7 6 Name Si 0 Default 0 0 Bit 0/Frame Alignment Signal Bit (1) Bit 1/Frame Alignment Signal Bit (1) Bit 2/Frame Alignment Signal Bit (0) ...
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Register Name: TAF Register Description: Transmit Align Frame Register Register Address: D0h Bit # 7 6 Name Si 0 Default 0 0 Bit 0/Frame Alignment Signal Bit (1) Bit 1/Frame Alignment Signal Bit (1) Bit 2/Frame Alignment Signal Bit (0) ...
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Method 3: Internal Register Scheme Based on CRC4 Multiframe The receive side contains a set of eight registers (RSiAF, RSiNAF, RRA, and RSa4–RSa8) that report the Si and Sa bits as they are received. These registers are updated with ...
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Register Name: RSiNAF Register Description: Received Si Bits of the Nonalign Frame Register Address: C9h Bit # 7 6 Name SiF1 SiF3 Default 0 0 Bit 0/Si Bit of Frame 15 (SiF15) Bit 1/Si Bit of Frame 13 (SiF13) Bit ...
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Register Name: RSa4 Register Description: Received Sa4 Bits Register Address: CBh Bit # 7 6 Name RSa4F1 RSa4F3 Default 0 0 Bit 0/Sa4 Bit of Frame 15 (RSa4F15) Bit 1/Sa4 Bit of Frame 13 (RSa4F13) Bit 2/Sa4 Bit of Frame ...
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Register Name: RSa6 Register Description: Received Sa6 Bits Register Address: CDh Bit # 7 6 Name RSa6F1 RSa6F3 Default 0 0 Bit 0/Sa6 Bit of Frame 15 (RSa6F15) Bit 1/Sa6 Bit of Frame 13 (RSa6F13) Bit 2/Sa6 Bit of Frame ...
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Register Name: RSa8 Register Description: Received Sa8 Bits Register Address: CFh Bit # 7 6 Name RSa8F1 RSa8F3 Default 0 0 Bit 0/Sa8 Bit of Frame 15 (RSa8F15) Bit 1/Sa8 Bit of Frame 13 (RSa8F13) Bit 2/Sa8 Bit of Frame ...
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Register Name: TSiNAF Register Description: Transmit Si Bits of the Nonalign Frame Register Address: D3h Bit # 7 6 Name TSiF1 TSiF3 Default 0 0 Bit 0/Si Bit of Frame 15 (TSiF15) Bit 1/Si Bit of Frame 13 (TSiF13) Bit ...
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Register Name: TSa4 Register Description: Transmit Sa4 Bits Register Address: D5h Bit # 7 6 Name TSa4F1 TSa4F3 Default 0 0 Bit 0/Sa4 Bit of Frame 15 (TSa4F15) Bit 1/Sa4 Bit of Frame 13 (TSa4F13) Bit 2/Sa4 Bit of Frame ...
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Register Name: TSa6 Register Description: Transmit Sa6 Bits Register Address: D7h Bit # 7 6 Name TSa6F1 TSa6F3 Default 0 0 Bit 0/Sa6 Bit of Frame 15 (TSa6F15) Bit 1/Sa6 Bit of Frame 13 (TSa6F13) Bit 2/Sa6 Bit of Frame ...
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Register Name: TSa8 Register Description: Transmit Sa8 Bits Register Address: D9h Bit # 7 6 Name TSa8F1 TSa8F3 Default 0 0 Bit 0/Sa8 Bit of Frame 15 (TSa8F15) Bit 1/Sa8 Bit of Frame 13 (TSa8F13) Bit 2/Sa8 Bit of Frame ...
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Register Name: TSACR Register Description: Transmit Sa Bit Control Register Register Address: DAh Bit # 7 6 Name SiAF SiNAF Default 0 0 Bit 0/Additional Bit 8 Insertion Control Bit (Sa8 not insert data from the TSa8 ...
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HDLC CONTROLLERS This device has two enhanced HDLC controllers, HDLC #1 and HDLC #2. Each controller is configurable for use with time slots, Sa4 to Sa8 bits (E1 mode), or the FDL (T1 mode). Each HDLC controller has 128-byte ...
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... Sa bits are used by the receive HDLC controller Selects which channels are mapped to the transmit HDLC controller Selects which bits in a channel are used or which Sa bits are used by the transmit HDLC controller FIFOs Access to 128-byte receive FIFO Access to 128-byte transmit FIFO 127 of 238 FUNCTION DS2155 ...
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Register Name: H1TC, H2TC Register Description: HDLC #1 Transmit Control HDLC #2 Transmit Control Register Address: 90h, A0h Bit # 7 6 Name NOFS TEOML Default 0 0 Bit 0/Transmit CRC Defeat (TCRCD). A 2-byte CRC code is automatically appended ...
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Register Name: H1RC, H2RC Register Description: HDLC #1 Receive Control HDLC #2 Receive Control Register Address: 31h, 32h Bit # 7 6 Name RHR RHMS Default 0 0 Bit 0/Receive SS7 Fill-In Signal Unit Delete (RSFD normal operation; ...
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FIFO Control The FIFO control register (HxFC) controls and sets the watermarks for the transmit and receive FIFOs. Bits 3, 4, and 5 set the transmit low watermark and the lower 3 bits set the receive high watermark. When ...
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HDLC Mapping 23.3.1 Receive The HDLC controllers must be assigned a space in the T1/E1 bandwidth in which they transmit and receive data. The controllers can be mapped to either the FDL (T1), Sa bits (E1 channels. ...
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Register Name: H1RTSBS, H2RTSBS Register Description: HDLC # 1 Receive Time Slot Bits/Sa Bits Select HDLC # 2 Receive Time Slot Bits/Sa Bits Select Register Address: 96h, A6h Bit # 7 6 Name RCB8SE RCB7SE Default 0 0 Bit 0/Receive ...
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Transmit The HxTCS1–HxTCS4 registers are used to assign the transmit controllers to channels 1–24 (T1) or 1–32 (E1) according to the following table. Register Channels HxTCS1 1–8 HxTCS2 9–16 HxTCS3 17–24 HxTCS4 25–32 Register Name: H1TCS1, H1TCS2, H1TCS3, H1TCS4 ...
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Register Name: H1TTSBS, H2TTSBS Register Description: HDLC # 1 Transmit Time Slot Bits/Sa Bits Select HDLC # 2 Transmit Time Slot Bits/Sa Bits Select Register Address: 9Bh, ABh Bit # 7 6 Name TCB8SE TCB7SE Default 0 0 Bit 0/Transmit ...
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Register Name: SR6, SR7 Register Description: HDLC #1 Status Register 6 HDLC #2 Status Register 7 Register Address: 20h, 22h Bit # 7 6 Name — TMEND Default 0 0 Bit 0/Transmit FIFO Not Full Condition (TNF). Set when the ...
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Register Name: IMR6, IMR7 Register Description: HDLC # 1 Interrupt Mask Register 6 HDLC # 2 Interrupt Mask Register 7 Register Address: 21h, 23h Bit # 7 6 Name — TMEND Default 0 0 Bit 0/Transmit FIFO Not Full Condition ...
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Register Name: INFO5, INFO6 Register Description: HDLC #1 Information Register HDLC #2 Information Register Register Address: 2Eh, 2Fh Bit # 7 6 Name — — Default 0 0 Bits 0 to 2/Receive Packet Status (PS0 to PS2). These are real-time ...
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FIFO Information The transmit FIFO buffer-available register indicates the number of bytes that can be written into the transmit FIFO. The count form this register informs the host as to how many bytes can be written into the transmit ...
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HDLC FIFOs Register Name: H1TF, H2TF Register Description: HDLC # 1 Transmit FIFO HDLC # 2 Transmit FIFO Register Address: 9Dh, ADh Bit # 7 6 Name THD7 THD6 Default 0 0 Bit 0/Transmit HDLC Data Bit 0 (THD0). ...
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... If enabled through T1RCR2.3, the DS2155 automatically looks for five row, followed finds such a pattern, it automatically removes the zero. If the zero destuffer sees six or more row followed the 0 is not removed ...
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Register Name: RFDL Register Description: Receive FDL Register Register Address: C0h Bit # 7 6 Name RFDL7 RFDL6 Default 0 0 The receive FDL register (RFDL) reports the incoming FDL or the incoming Fs bits. The LSB is received first. ...
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Transmit Section The transmit section shifts out into the T1 data stream either the FDL (in the ESF framing mode) or the Fs bits (in the D4 framing mode) contained in the transmit FDL register (TFDL). When a new ...
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... The DS2155 has the option of using software-selectable termination requiring only a single fixed pair of termination resistors. The DS2155’s LIU is designed to be fully software selectable for E1 and T1, requiring no change to any external resistors for the receive side. The receive side allows the user to configure the DS2155 for 75Ω, 100Ω ...
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... LSB (2.5dB) from 25C to 85C and +/- 2 LSB’s (5dB) from –40C to 25C. 24.2.2 Receive G.703 Synchronization Signal (E1 Mode) The DS2155 is capable of receiving a 2.048MHz square-wave synchronization clock as specified in Section 13 of ITU G.703, October 1998. In order to use the DS2155 in this mode, set the receive synchronization clock enable (LIC3. 24.2.3 Monitor Mode Monitor applications in both E1 and T1 require various flat gain settings for the receive-side circuitry ...
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... TCLK. Also, the waveforms created are independent of the duty cycle of TCLK. The transmitter in the DS2155 couples to the transmit twisted pair (or coaxial cable in some E1 applications) through a 1:2 step-up transformer. For the device to create the proper waveforms, the transformer used must meet the specifications listed in option of using software-selectable transmit termination ...
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... PLL. 24.5 Jitter Attenuator The DS2155 contains an on-board jitter attenuator that can be set to a depth of either 32 or 128 bits through the JABDS bit (LIC1.2). The 128-bit mode is used in applications where large excursions of wander are expected. The 32-bit mode is used in delay-sensitive applications. The characteristics of the ...
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LIU Control Registers Register Name: LIC1 Register Description: Line Interface Control 1 Register Address: 78h Bit # 7 6 Name L2 L1 Default 0 0 Bit 0/Transmit Power-Down (TPD powers down the transmitter and tri-states the TTIP ...
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T1 Mode DSX-1 (0ft to 133ft) / 0dB CSU DSX-1 (133ft to 266ft DSX-1 (266ft to 399ft DSX-1 (399ft to 533ft DSX-1 ...
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Register Name: TLBC Register Description: Transmit Line Build-Out Control Register Address: 7Dh Bit # 7 6 Name - AGCE Default 0 0 Bit 0–5 Gain Control Bits 0–5 (GC0–GC5). The GC0 through GC5 bits control the gain setting for the ...
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Register Name: LIC2 Register Description: Line Interface Control 2 Register Address: 79h Bit # 7 6 Name ETS LIRST Default 0 0 Bit 0/Custom Line Driver Select (CLDS). Setting this bit redefines the operation of the transmit ...
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Register Name: LIC3 Register Description: Line Interface Control 3 Register Address: 7Ah Bit # 7 6 Name — TCES Default 0 0 Bit 0/Transmit Alternate Ones and Zeros (TAOZ). Transmit a …101010… pattern (customer disconnect indication signal) at TTIP and ...
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Register Name: LIC4 Register Description: Line Interface Control 4 Register Address: 7Bh Bit # 7 6 Name CMIE CMII Default 0 0 Bits 0, 1/Receive Termination Select (RT0, RT1) RT1 RT0 Internal Receive-Termination Configuration 0 0 Internal receive-side termination disabled ...
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Register Name: INFO2 Register Description: Information Register 2 Register Address: 11h Bit # 7 6 Name BSYNC BD Default 0 0 Bits 0 to 3/Receive Level Bits (RL0 to RL3). Real-time bits RL3 RL2 RL1 ...
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Register Name: SR1 Register Description: Status Register 1 Register Address: 16h Bit # 7 6 Name ILUT TIMER Default 0 0 Bit 0/Loss of Line-Interface Transmit-Clock Condition (LOLITC). Set when TCLKI has not transitioned for one channel time. This is ...
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Register Name: IMR1 Register Description: Interrupt Mask Register 1 Register Address: 17h Bit # 7 6 Name ILUT TIMER Default 0 0 Bit 0/Loss-of-Transmit Clock Condition (LOLITC interrupt masked 1 = interrupt enabled—generates interrupts on rising and falling ...
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... Note 4: A list of transformer part numbers and manufacturers is available by contacting telecom.support@dalsemi.com. 1.0 µ 2 1:1 60 Ω 60 Ω 0.1 µF DESCRIPTION 156 of 238 DS2155 TTIP DVDD 2 0.01 µF DVSS TRING Dallas Semiconductor T1/E1/J1 SCT or LIU RTIP TVDD 0.1 µF 2 TVSS RRING RVDD 0.1 µF 2 RVSS VCC 2 0.1 µ ...
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Figure 24-4. Software-Selected Termination, Longitudinal Protection F1 100/110/120 Ω isted Pair F2 F3 100/110/120 Ω isted Pair F4 Design Notes: 1 Choke is optional but should be included when necessary f or common mode noise reduction. ...
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Component Specifications Table 24-C. Transformer Specifications SPECIFICATION Turns Ratio 3.3V Applications Primary Inductance Leakage Inductance Intertwining Capacitance Transmit Transformer DC Resistance Primary (Device Side) Secondary Receive Transformer DC Resistance Primary (Device Side) Secondary RECOMMENDED VALUE 1:1 (receive) and 1:2 ...
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Figure 24-5. E1 Transmit Pulse Template 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -250 Figure 24-6. T1 Transmit Pulse Template 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 ...
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... Figure 24-7. Jitter Tolerance 1k 100 10 1 0.1 1 Figure 24-8. Jitter Tolerance (E1 Mode) 1k 100 0.1 1 DS2155 TOLERANCE TR 62411 (DEC. 90) ITU-T G.823 10 100 1k FREQUENCY (Hz) DS2155 TOLERANCE 1.5 MINIMUM TOLERANCE LEVEL AS PER ITU G.823 20 10 100 1k FREQUENCY (Hz) 160 of 238 10k 100k 0.2 2.4k 18k 10k 100k ...
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... Figure 24-9. Jitter Attenuation (T1 Mode) 0dB -20dB -40dB -60dB 1 Figure 24-10. Jitter Attenuation (E1 Mode) 0 -20 -40 -60 1 DS2155 T1 MODE 10 100 1K FREQUENCY (Hz) TBR12 Prohibited Area DS2155 E1 MODE 10 100 1k FREQUENCY (Hz) 161 of 238 TR 62411 (Dec. 90) Prohibited Area 10K 100K ITU G.7XX Prohibited Area 10k 100k ...
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... Figure 24-11. Optional Crystal Connections Note 1: C1 and C2 should be 5pF lower than two times the nominal loading capacitance of the crystal to adjust for the input capacitance of the DS2155. DS2155 XTALD MCLK C1 C2 162 of 238 1.544MHz/2.048MHz ...
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... PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION The DS2155 has the ability to generate and detect a repeating bit pattern from one to eight bits or 16 bits in length. This function is available only in T1 mode. To transmit a pattern, the user loads the pattern into the transmit code-definition registers (TCD1 and TCD2) and selects the proper length of the pattern by setting the TC0 and TC1 bits in the in-band code control (IBCC) register ...
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Register Name: IBCC Register Description: In-Band Code Control Register Register Address: B6h Bit # 7 6 Name TC1 TC0 Default 0 0 Bits 0 to 2/Receive Down-Code Length Definition Bits (RDN0 to RDN2) RDN2 RDN1 ...
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Register Name: TCD1 Register Description: Transmit Code-Definition Register 1 Register Address: B7h Bit # 7 6 Name C7 C6 Default 0 0 Bit 0/Transmit Code-Definition Bit 0 (C0). A don’t care if a 5-, 6-, or 7-bit length is selected. ...
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Register Name: RUPCD1 Register Description: Receive Up-Code Definition Register 1 Register Address: B9h Bit # 7 6 Name C7 C6 Default 0 0 Note: Writing this register resets the detector’s integration period. Bit 0/Receive Up-Code Definition Bits 0 (C0). A ...
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Register Name: RDNCD1 Register Description: Receive Down-Code Definition Register 1 Register Address: BBh Bit # 7 6 Name C7 C6 Default 0 0 Note: Writing this register resets the detector’s integration period. Bit 0/Receive Down-Code Definition Bit 0 (C0). A ...
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Register Name: RSCC Register Description: In-Band Receive Spare Control Register Register Address: BDh Bit # 7 6 Name — — Default 0 0 Bits 0 to 2/Receive Spare Code Length Definition Bits (RSC0 to RSC2) RSC2 RSC1 RSC0 0 0 ...
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Register Name: RSCD1 Register Description: Receive Spare-Code Definition Register 1 Register Address: BEh Bit # 7 6 Name C7 C6 Default 0 0 Note: Writing this register resets the detector’s integration period. Bit 0/Receive Spare-Code Definition Bit 0 (C0). A ...
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BERT FUNCTION The BERT block can generate and detect pseudorandom and repeating bit patterns used to test and stress data communication links, and it is capable of generating and detecting the following patterns: The pseudorandom patterns 2E7, ...
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Figure 26-1. Simplified Diagram of BERT in Network Direction FROM RECEIVE FRAMER PER-CHANNEL AND F-BIT (T1 MODE) MAPPING TO TRANSMIT FRAMER Figure 26-2. Simplified Diagram of BERT in Backplane Direction FROM RECEIVE FRAMER PER-CHANNEL AND F-BIT (T1 MODE) MAPPING TO ...
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BERT Register Descriptions Register Name: BC1 Register Description: BERT Control Register 1 Register Address: E0h Bit # 7 6 Name TC TINV Default 0 0 Bit 0/Force Resynchronization (RESYNC). A low-to-high transition forces the receive BERT synchronizer to resynchronize ...
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Register Name: BC2 Register Description: BERT Control Register 2 Register Address: E1h Bit # 7 6 Name EIB2 EIB1 Default 0 0 Bits 0 to 3/Repetitive Pattern Length Bit 3 (RPL0 to RPL3). RPL0 is the LSB and RPL3 is ...
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Register Name: SR9 Register Description: Status Register 9 Register Address: 26h Bit # 7 6 Name — BBED Default 0 0 Bit 0/BERT in Synchronization Condition (BSYNC). Set when the incoming pattern matches for 32 consecutive bit positions. Refer to ...
Page 175
Register Name: IMR9 Register Description: Interrupt Mask Register 9 Register Address: 27h Bit # 7 6 Name — BBED Default 0 0 Bit 0/BERT in Synchronization Condition (BSYNC interrupt masked 1 = interrupt enabled—interrupts on rising and falling ...
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BERT Repetitive Pattern Set These registers must be properly loaded for the BERT to generate and synchronize to a repetitive pattern, a pseudorandom pattern, alternating word pattern Daly pattern. For a repetitive pattern that is fewer than ...
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BERT Bit Counter Once BERT has achieved synchronization, this 32-bit counter increments for each data bit (i.e., clock) received. Toggling the LC control bit in BC1 can clear this counter. This counter saturates when full and sets the BBCO ...
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BERT Error Counter Once BERT has achieved synchronization, this 24-bit counter increments for each data bit received in error. Toggling the LC control bit in BC1 can clear this counter. This counter saturates when full and sets the BECO ...
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Register Name: BIC Register Description: BERT Interface Control Register Register Address: EAh Bit # 7 6 Name — RFUS Default 0 0 Bit 0/BERT Enable (BERTEN BERT disabled 1 = BERT enabled Bit 1/BERT Direction (BERTDIR ...
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... PAYLOAD ERROR-INSERTION FUNCTION (T1 MODE ONLY) An error-insertion function is available in the DS2155 and is used to create errors in the payload portion of the T1 frame in the transmit path. This function is only available in T1 mode. Errors can be inserted over the entire frame or the user can select which channels are to be corrupted. Errors are created by inverting the last bit in the count sequence ...
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Register Name: ERC Register Description: Error-Rate Control Register Register Address: EBh Bit # 7 6 Name WNOE — Default 0 0 Bits 0 to 3/Error-Insertion Rate Select Bits (ER0 to ER3) ER3 ER2 ER1 ER0 ...
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Number-of-Errors Registers The number-of-error registers determine how many errors are generated 1023 errors can be generated. The host loads the number of errors to be generated into the NOE1 and NOE2 registers. The host can also update ...
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Number-of-Errors Left Register The host can read the NOELx registers at any time to determine how many errors are left to be inserted. Register Name: NOEL1 Register Description: Number-of-Errors Left 1 Register Address: EEh Bit # 7 6 Name ...
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... In channel interleave mode, data is output to the PCM data-out bus one channel at a time from each of the connected DS2155s until all channels of frame n from each DS2155 have been placed on the bus. This mode can be used even when the DS2155s are operating asynchronous to each other. The elastic stores ...
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Register Name: IBOC Register Description: Interleave Bus Operation Control Register Register Address: C5h Bit # 7 6 Name — IBS1 Default 0 0 Bits 0 to 2/Device Assignment Bits (DA0 to DA2) DA2 DA1 DA0 ...
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... TSIG TSER DS2155 #2 RSER RSYSCLK TSYSCLK RSYNC TSSYNC RSIG TSIG TSER DS2155 #3 RSER RSYSCLK TSYSCLK RSYNC TSSYNC RSIG TSIG TSER DS2155 #4 RSER 186 of 238 8.192MHz SYSTEM CLOCK IN SYSTEM 8kHz FRAME SYNC IN PCM SIGNALING OUT PCM SIGNALING IN PCM DATA IN PCM DATA OUT ...
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... ESIBCR2) and four information registers (ESIB1, ESIB2, ESIB3, and ESIB4). For example, eight DS2155s can be grouped into an ESIB group. A single read of the ESIB1 register of any member of the group yields the interrupt status of all eight DS2155s. Therefore, the host can determine which device or devices are causing an interrupt without polling all eight devices ...
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... Bits 1 to 3/Output Data Bus Line Select (ESIBSEL0 to ESIBSEL2). These bits tell the DS2155 what data bus bit to output the ESIB data on when one of the ESIB information registers is accessed. Each member of the ESIB group must have a unique bit selected. ...
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... Bit 3/Unused, must be set to 0 for proper operation Bits 4 to 6/Address ESI4 Data-Output Select (ESI4SEL0 to ESI4SEL2). These bits select what status output when the DS2155 decodes an ESI4 address during a bus read operation. ESI4SEL2 ESI4SEL1 ESI4SEL0 ...
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Register Name: ESIB1 Register Description: Extended System Information Bus Register 1 Register Address: B2h Bit # 7 6 Name DISn DISn Default 0 0 Bits 0 to 7/Device Interrupt Status (DISn). Causes all devices participating in the ESIB group to ...
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... Bits Unused, must be set to 0 for proper operation 31. FRACTIONAL T1/E1 SUPPORT The DS2155 can be programmed to output gapped clocks for selected channels in the receive and transmit paths to simplify connections into a USART or LAPD controller in fractional T1/E1 or ISDN- PRI applications. The receive and transmit paths have independent enables. Channel formats supported include 56kbps and 64kbps ...
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Register Name: CCR3 Register Description: Common Control Register 3 Register Address: 72h Bit # 7 6 Name TMSS INTDIS Default 0 0 Bit 0/Receive Gapped-Clock Enable (RGPCKEN RCHCLK functions normally 1 = enable gapped bit-clock output on RCHCLK ...
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... USER-PROGRAMMABLE OUTPUT PINS The DS2155 provides four user-programmable output pins. The pins are automatically cleared power- result of a hardware- or software-issued reset. Register Name: CCR4 Register Description: Common Control Register 4 Register Address: 73h Bit # 7 6 Name RLT3 RLT2 Default 0 0 Bit 0/User-Defined Output 0 (UOP0) ...
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TRANSMIT FLOW DIAGRAMS Figure 33-1. T1 Transmit Flow Diagram HSIE1-3 through PCPR ESCR.4 TESE LBCR1.1 PLB TLINK H1TC.4 HDLC FDL #1 THMS1 H2TC.4 HDLC FDL #2 THMS2 TFDL Tx FDL T1TCR2.5 Zero TZSE Stuffer T1TCR1.2 FDL Mux TFDLS BOC ...
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From BOC Mux T1TCR2.3 FBCT1 T1TCR2.4 FBCT2 NOEL != 0 ERC.4 CE PEICS1-3 T1CCR1.1 PDE CRC Calculation T1TCR2.7 B8ZSE T1TCR1.1 TBL IOCR1.0 ODF CCR1.4 ODM From ESF Yellow Alarm FDL Mux ESF Yellow CRC Mux D4 bit 2 BERT Yellow ...
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Figure 33-2. E1 Transmit Flow Diagram HSIE1-4 through PCPR ESCR.4 TESE LBCR1.1 PLB KEY - PIN - SELECTOR - REGISTER TSER TSIG Hardware Signaling TX ESTORE Estore Mux TESO Off-Chip Connection TDATA RDATA From E1_rcv_logic Payload HDLC Loopback Mux Engine ...
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From Idle Code Mux Per-Channel TNAF Sa-bit Mux Si-bit Mux E1TCR1.4 TSIS E1TCR1.0 TCRC4 Si/CRC4 Mux Auto E- E1TCR2.2 AEBE bit Gen Sa4S - Sa8S E1TCR2.5 - E1TCR2.7 E1TCR2.8 ARA TSaCR SSIE1-4 E1TCR1.0 T16S E1TCR1.0 TCRC4 CCR1.6 CRC4R E1TCR2.1 AAIS ...
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From HDB3 Encoding Mux Bipolar/ NRZ IOCR1.0 ODF coding RPOS RLB Mux CCR1.4 ODM TPOS FLB LBCR1.0 FLB TO RECEIVER Select RNEG RLB Mux RLB LBCR1.2 1/2 CLK/ FULL CLK TNEG 198 of 238 E1 TRANSMIT FLOW DIAGRAM ...
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... Boundary Scan Register Device Identification Register The DS2155 is pin-compatible with the DS2152, DS21x52 (T1) and DS2154, DS21x54 (E1) SCT families. The JTAG feature uses pins that had no function in the DS2152 and DS2154. Details about boundary scan architecture and the TAP are in IEEE 1149.1-1990, IEEE 1149.1a-1993, and IEEE 1149 ...
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TAP Controller State Machine The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK (Figure 34-2). Test-Logic-Reset Upon power-up, the TAP controller is in the Test-Logic-Reset state. The ...