DS21552L+ Maxim Integrated Products, DS21552L+ Datasheet - Page 24

• Manufacturer Part Number: DS21552L+
• Description: IC TXRX T1 1-CHIP 5V 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21552L+

• Function: Single-Chip Transceiver
• Interface: E1, HDLC, J1, T1
• Number Of Circuits: 1
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: DSX-1 and CSU Line Build-Out Generator, HDLC Controller, In-Band Loop Code Generator and Detector
• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 64 Kbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 75 mA (Typ)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Ic Interface Type: Parallel, Serial
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 100
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.1.6 LINE INTERFACE PINS
Signal Name:
Signal Description:
Signal Type:
A 1.544 MHz (50 ppm) clock source with TTL levels is applied at this pin. This clock is used internally for both clock/data
recovery and for jitter attenuation. A quartz crystal of 1.544 MHz may be applied across MCLK and XTALD instead of the
TTL level clock source.
Signal Name:
Signal Description:
Signal Type:
A quartz crystal of 1.544 MHz may be applied across MCLK and XTALD instead of a TTL level clock source at MCLK.
Leave open circuited if a TTL clock source is applied at MCLK.
Signal Name:
Signal Description:
Signal Type:
A 12.352 MHz clock that is locked to the 1.544 MHz clock provided from the clock/data recovery block (if the jitter attenuator
is enabled on the receive side) or from the TCLKI pin (if the jitter attenuator is enabled on the transmit side). Can be internally
disabled by writing a 08h to TEST2.3 if not needed.
Signal Name:
Signal Description:
Signal Type:
Tie low to separate the line interface circuitry from the framer/formatter circuitry and activate the
TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/ RCLKI pins. Tie high to connect the line interface circuitry to the framer/formatter
circuitry and deactivate the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins. When LIUC is tied high, the
TPOSI/TNEGI/TCLKI/ RPOSI/RNEGI/RCLKI pins should be tied low.
Signal Name:
Signal Description:
Signal Type:
Analog inputs for clock recovery circuitry. These pins connect via a 1:1 transformer to the T1 line. See Section 16 for details.
Signal Name:
Signal Description:
Signal Type:
Analog line driver outputs. These pins connect via a transformer to the T1 line. See Section 16 for details.
MCLK
Master Clock Input
Input
XTALD
Quartz Crystal Driver
Output
8XCLK
Eight Times Clock
Output
LIUC
Line Interface Connect
Input
RTIP & RRING
Receive Tip and Ring
Input
TTIP & TRING
Transmit Tip and Ring
Output
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