DS21552L+ Maxim Integrated Products, DS21552L+ Datasheet - Page 47
DS21552L+
Manufacturer Part Number
DS21552L+
Description
IC TXRX T1 1-CHIP 5V 100-LQFP
Manufacturer
Maxim Integrated Products
Datasheet
1.DS21352L.pdf
(137 pages)
Specifications of DS21552L+
Function
Single-Chip Transceiver
Interface
E1, HDLC, J1, T1
Number Of Circuits
1
Voltage - Supply
4.75 V ~ 5.25 V
Current - Supply
75mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-LQFP
Includes
DSX-1 and CSU Line Build-Out Generator, HDLC Controller, In-Band Loop Code Generator and Detector
Product
Framer
Number Of Transceivers
1
Data Rate
64 Kbps
Supply Voltage (max)
3.465 V
Supply Voltage (min)
3.135 V
Supply Current (max)
75 mA (Typ)
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Ic Interface Type
Parallel, Serial
Supply Voltage Range
4.75V To 5.25V
Operating Temperature Range
0°C To +70°C
Digital Ic Case Style
LQFP
No. Of Pins
100
Filter Terminals
SMD
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Table 7-2 ALARM CRITERIA
Blue Alarm (AIS) (see note 1
below)
Yellow Alarm (RAI)
1. D4 bit 2 mode(RCR2.2=0)
2. D4 12th F–bit mode
(RCR2.2=1; this mode is also
referred to as the “Japanese
Yellow Alarm”)
3. ESF mode
Red Alarm (LRCL) (this alarm
is also referred to as Loss Of
Signal)
NOTES:
1. The definition of Blue Alarm (or Alarm Indication Signal) is an unframed all ones signal. Blue alarm detectors should be
able to operate properly in the presence of a 10E–3 error rate and they should not falsely trigger on a framed all ones signal.
The blue alarm criteria in the DS21352/552 has been set to achieve this performance. It is recommended that the RBL bit be
qualified with the RLOS bit.
2. ANSI specifications use a different nomenclature than the DS21352/552 does; the following terms are equivalent:
ALARM
RBL = AIS
RCL = LOS
RLOS = LOF
RYEL = RAI
when over a 3 ms window, 5 or
less zeros are received
when bit 2 of 256 consecutive
channels is set to zero for at least
254 occurrences
when the 12th framing bit is set
to one for two consecutive
occurrences
when 16 consecutive patterns of
00FF appear in the FDL
when 192 consecutive zeros are
received
SET CRITERIA
47 of 137
when over a 3 ms window, 6 or more zeros are
received
when bit 2 of 256 consecutive channels is set to
zero for less than 254 occurrences
when the 12th framing bit is set to zero for two
consecutive occurrences
when 14 or less patterns of 00FF hex out of 16
possible appear in the FDL
when 14 or more ones out of 112 possible bit
positions are received starting with the first one
received
CLEAR CRITERIA
DS21352/DS21552
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