DS21552L+ Maxim Integrated Products, DS21552L+ Datasheet - Page 55

• Manufacturer Part Number: DS21552L+
• Description: IC TXRX T1 1-CHIP 5V 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21552L+

• Function: Single-Chip Transceiver
• Interface: E1, HDLC, J1, T1
• Number Of Circuits: 1
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: DSX-1 and CSU Line Build-Out Generator, HDLC Controller, In-Band Loop Code Generator and Detector
• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 64 Kbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 75 mA (Typ)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Ic Interface Type: Parallel, Serial
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 100
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TDS0M: TRANSMIT DS0 MONITOR REGISTER (Address=1A Hex)
CCR6: COMMON CONTROL REGISTER 6 (Address=1E Hex)
[repeated here from section 6 for convenience]
RDS0M: RECEIVE DS0 MONITOR REGISTER (Address=1F Hex
SYMBOL
SYMBOL
SYMBOL
(MSB)
(MSB)
(MSB)
RCM4
RCM3
RCM2
RCM1
RCM0
RJC
RESA
TESA
B1
B1
RJC
B1
B2
B3
B4
B5
B6
B7
B8
B1
B2
B3
B4
RESA
POSITION
POSITION
POSITION
RDS0M.7
RDS0M.6
RDS0M.5
RDS0M.4
TDS0M.7
TDS0M.6
TDS0M.5
TDS0M.4
TDS0M.3
TDS0M.2
TDS0M.1
TDS0M.0
B2
B2
CCR6.7
CCR6.6
CCR6.5
CCR6.4
CCR6.3
CCR6.2
CCR6.1
CCR6.0
TESA
NAME AND DESCRIPTION
Transmit DS0 Channel Bit 1. MSB of the DS0 channel (first bit to be transmitted).
Transmit DS0 Channel Bit 2.
Transmit DS0 Channel Bit 3.
Transmit DS0 Channel Bit 4.
Transmit DS0 Channel Bit 5.
Transmit DS0 Channel Bit 6.
Transmit DS0 Channel Bit 7.
Transmit DS0 Channel Bit 8. LSB of the DS0 channel (last bit to be transmitted).
NAME AND DESCRIPTION
Receive Japanese CRC Enable.
Receive Elastic Store Align.
Transmit Elastic Store Align.
Receive Channel Monitor Bit 4. MSB of a channel decode that determines which
receive DS0 channel data will appear in the RDS0M register.
Receive Channel Monitor Bit 3.
Receive Channel Monitor Bit 2.
Receive Channel Monitor Bit 1.
Receive Channel Monitor Bit 0. LSB of the channel decode that determines which
receive DS0 channel data will appear in the RDS0M register.
NAME AND DESCRIPTION
Receive DS0 Channel Bit 1. MSB of the DS0 channel (first bit to be received).
Receive DS0 Channel Bit 2.
Receive DS0 Channel Bit 3.
Receive DS0 Channel Bit 4.
B3
B3
RCM4
B4
B4
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RCM3
B5
B5
RCM2
B6
B6
RCM1
B7
B7
)
RCM0
(LSB)
(LSB)
B8
(LSB)
B8