DS21552L+ Maxim Integrated Products, DS21552L+ Datasheet - Page 33

• Manufacturer Part Number: DS21552L+
• Description: IC TXRX T1 1-CHIP 5V 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21552L+

• Function: Single-Chip Transceiver
• Interface: E1, HDLC, J1, T1
• Number Of Circuits: 1
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: DSX-1 and CSU Line Build-Out Generator, HDLC Controller, In-Band Loop Code Generator and Detector
• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 64 Kbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 75 mA (Typ)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Ic Interface Type: Parallel, Serial
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 100
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TCR1: TRANSMIT CONTROL REGISTER 1 (Address=35 Hex)
NOTE: For a description of how the bits in TCR1 affect the transmit side formatter, see Figure 22-2
LOTCMC
SYMBOL
LOTCMC
(MSB)
TFDLS
TYEL
TCPT
GB7S
TFPT
TSSE
TBL
TFPT
POSITION
TCR1.7
TCR1.6
TCR1.5
TCR1.4
TCR1.3
TCR1.2
TCR1.1
TCR1.0
TCPT
NAME AND DESCRIPTION
Loss Of Transmit Clock Mux Control. Determines whether the transmit side
formatter should switch to RCLK if the TCLK input should fail to transition.
0 = do not switch to RCLK if TCLK stops
1 = switch to RCLK if TCLK stops
Transmit F–Bit Pass Through. (see note below)
0 = F bits sourced internally
1 = F bits sampled at TSER
Transmit CRC Pass Through. (see note below)
0 = source CRC6 bits internally
1 = CRC6 bits sampled at TSER during F–bit time
Transmit Software Signaling Enable. (see note below)
0 = no signaling is inserted in any channel
1 = signaling is inserted in all channels from the TS1-TS12 registers (the TTR registers
can be used to block insertion on a channel by channel basis)
Global Bit 7 Stuffing. (see note below)
0 = allow the TTR registers to determine which channels containing all zeros are to be
Bit 7 stuffed
1 = force Bit 7 stuffing in all zero byte channels regardless of how the TTR registers are
programmed
TFDL Register Select. (see note below)
0 = source FDL or Fs bits from the internal TFDL register (legacy FDL support mode)
1 = source FDL or Fs bits from the internal HDLC/BOC controller or the TLINK pin
Transmit Blue Alarm. (see note below)
0 = transmit data normally
1 = transmit an unframed all one’s code at TPOSO and TNEGO
Transmit Yellow Alarm. (see note below)
0 = do not transmit yellow alarm
1 = transmit yellow alarm
TSSE
33 of 137
GB7S
TFDLS
TBL
(LSB)
TYEL