LPC1857FET256,551 NXP Semiconductors, LPC1857FET256,551 Datasheet - Page 974

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LPC1857FET256,551

Manufacturer Part Number
LPC1857FET256,551
Description
IC MCU 32BIT 1MB FLASH 256LBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr

Specifications of LPC1857FET256,551

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LPC1857FET256,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
<Document ID>
User manual
Table 921. DMA muxing register (DMAMUX, address 0x4004 311C) bit description
Bit
7:6
9:8
11:10
13:12
15:14
17:16
Symbol
DMAMUXCH3
DMAMUXCH4
DMAMUXCH5
DMAMUXCH6
DMAMUXCH7
DMAMUXCH8
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Value
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
Description
selects DMA to peripheral connection for
DMA peripheral 3:
Timer 1, match channel 0
UART1 transmit
Reserved
Reserved
selects DMA to peripheral connection for
DMA peripheral 4:
Timer 1, match channel 1
UART1 receive
Reserved
Reserved
selects DMA to peripheral connection for
DMA peripheral 5:
Timer 2, match channel 0
USART2 transmit
Reserved
Reserved
selects DMA to peripheral connection for
DMA peripheral 6:
Timer 2, match channel 1
USART2 receive
Reserved
Reserved
selects DMA to peripheral connection for
DMA peripheral 7:
Timer 3, match channel 0
USART3 transmit
SCT output 0
Reserved
selects DMA to peripheral connection for
DMA peripheral 8:
Timer 3, match channel 1
USART3 receive
SCT output 1
Reserved
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
0
0
0
0
0
…continued
974 of 1164
Access
R/W
R/W
R/W
R/W
R/W
R/W

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