LPC1857FET256,551 NXP Semiconductors, LPC1857FET256,551 Datasheet - Page 378

• Manufacturer Part Number: LPC1857FET256,551
• Description: IC MCU 32BIT 1MB FLASH 256LBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1857FET256,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
Table 323. USB BINTERVAL register (BINTERVAL - address 0x4000 6174) bit description
Table 324. USB endpoint NAK register (ENDPTNAK - address 0x4000 6178) bit description
<Document ID>
User manual
Bit
3:0
31:4
Bit
5:0
15:6
21:16 EPTN
31:22 -
Symbol
BINT
-
Symbol
EPRN
-
20.6.13.1 Device mode
20.6.13.2 Host mode
20.6.14.1 Device mode
20.6.13 USB Endpoint NAK register (ENDPTNAK)
20.6.14 USB Endpoint NAK Enable register (ENDPTNAKEN)
This register indicates when the device sends a NAK handshake on an endpoint. Each Tx
and Rx endpoint has a bit in the EPTN and EPRN field respectively.
A bit in this register is cleared by writing a 1 to it.
This register is not used in host mode.
Each bit in this register enables the corresponding bit in the ENDPTNAK register. Each Tx
and Rx endpoint has a bit in the EPTNE and EPRNE field respectively.
Description
bInterval value (see
reserved
Description
Rx endpoint NAK
Each RX endpoint has one bit in this field. The bit is set when the device
sends a NAK handshake on a received OUT or PING token for the
corresponding endpoint.
Bit 5 corresponds to endpoint 5.
...
Bit 1 corresponds to endpoint 1.
Bit 0 corresponds to endpoint 0.
Reserved
Tx endpoint NAK
Each TX endpoint has one bit in this field. The bit is set when the device
sends a NAK handshake on a received IN token for the corresponding
endpoint.
Bit 3 corresponds to endpoint 3.
...
Bit 1 corresponds to endpoint 1.
Bit 0 corresponds to endpoint 0.
reserved
All information provided in this document is subject to legal disclaimers.
Section
Rev. 00.13 — 20 July 2011
20.7.7)
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
UM10430
© NXP B.V. 2011. All rights reserved.
-
Reset
value
0x00
-
Reset
value
0x00
-
0x00
378 of 1164
Access
R/W
-
Access
R/WC
-
R/WC
-