LPC1857FET256,551 NXP Semiconductors, LPC1857FET256,551 Datasheet - Page 587
LPC1857FET256,551
Manufacturer Part Number
LPC1857FET256,551
Description
IC MCU 32BIT 1MB FLASH 256LBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1857FET256,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1857FET256,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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24.1 How to read this chapter
24.2 Basic configuration
24.3 Features
<Document ID>
User manual
The SCT is available on all LPC18xx parts.
The following configuration options apply to parts LPC1850_30_20_10 Rev ‘A’ only:
The SCT is configured as follows:
Table 497. SCT clocking and power control
SCT
•
•
•
•
•
•
•
•
•
•
•
•
•
•
UM10430
Chapter 24: LPC18xx State Configurable Timer (SCT)
Rev. 00.13 — 20 July 2011
The SCT inputs and outputs are connected to event-driven peripherals through the
GIMA (see
See
The SCT is reset by the SCT_RST (reset #37).
Connect inputs and outputs of the SCT through the GIMA (see
The SCT combined interrupt is connected to slot # 10 in the NVIC. SCT outputs 2, 6,
14 are ORed with timer match channels and connected to slots # 13, 14, 16 in the
Event router (see
For connecting the SCT outputs 0 and 1 to the GPDMA, use the DMAMUX register in
the CREG block (see
Configuration registers
Two 16-bit counters or one 32-bit counter.
Counter(s) clocked by bus clock or selected input.
Up counter(s) or up-down counter(s).
State variable allows sequencing across multiple counter cycles.
Event can be defined by a counter match condition, an input (or output) condition, a
combination of a match and/or and input/output condition in a specified state.
Events control outputs, interrupts, and DMA requests.
Selected event(s) can limit, halt, start, or stop a counter.
Supports:
– 8 inputs
– 16 outputs
– 16 match/capture registers
– 16 events
Table 497
Base clock
BASE_M3_CLK
Section
All information provided in this document is subject to legal disclaimers.
for clocking and power control.
Table
Rev. 00.13 — 20 July 2011
14.3).
Table
Section
16).
35) and enable the GPDMA channel in the DMA Channel
16.6.20.
Branch clock
CLK_M3_SCT
Chapter
Maximum frequency
150 MHz
© NXP B.V. 2011. All rights reserved.
User manual
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