LPC1857FET256,551 NXP Semiconductors, LPC1857FET256,551 Datasheet - Page 906
LPC1857FET256,551
Manufacturer Part Number
LPC1857FET256,551
Description
IC MCU 32BIT 1MB FLASH 256LBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1857FET256,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1857FET256,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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39.1 How to read this chapter
39.2 Basic configuration
39.3 Features
39.4 Pin description
<Document ID>
User manual
The DAC is available on all LPC18xx parts.
The DAC is configured as follows:
Table 834. DAC clocking and power control
Table 835
Table 835. DAC pin description
Clock to the DAC register
interface and rate clock for the
DMA counter.
Pin
ADC0
VDDA
VSSA
•
•
•
•
•
•
•
•
UM10430
Chapter 39: LPC18xx DAC
Rev. 00.13 — 20 July 2011
See
The DAC is reset by the DAC_RST (reset # 42).
The DAC interrupt is connected to interrupt slot # 0 in the NVIC.
For connecting to the GPDMA, use the DMAMUX register
block and enable the GPDMA channel in the DMA Channel Configuration registers
Section
10-bit resolution
Monotonic by design (resistor string architecture)
Controllable conversion speed
Low power consumption
Table 834
gives a brief summary of each of DAC related pins.
16.6.20.
Type
Output
Power
-
All information provided in this document is subject to legal disclaimers.
for clocking and power control.
Rev. 00.13 — 20 July 2011
Description
Analog Output. After the selected settling time after the DACR is
written with a new value, the voltage on this pin (with respect to
V
channel 0 input pin of ADC0 and ADC1.
Analog power and voltage reference. This pin provides a voltage
reference level for the D/A converter.
Ground.
SSA
Base clock
BASE_APB3_CLK CLK_APB3_DAC
) is VALUE/1024 VREF. The DACOUT pin is shared with the
Branch clock
(Table
Maximum
frequency
150 MHz
35) in the CREG
© NXP B.V. 2011. All rights reserved.
User manual
Notes
-
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