LPC1857FET256,551 NXP Semiconductors, LPC1857FET256,551 Datasheet - Page 285
LPC1857FET256,551
Manufacturer Part Number
LPC1857FET256,551
Description
IC MCU 32BIT 1MB FLASH 256LBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1857FET256,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1857FET256,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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Table 217. Endian behavior
<Document ID>
User manual
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16.7.1.6.3 Error conditions
16.7.1.7 Channel hardware
16.7.1.8 DMA request priority
16.7.1.9 Interrupt generation
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An error during a DMA transfer is flagged directly by the peripheral by asserting an Error
response on the AHB bus during the transfer. The DMA Controller automatically disables
the DMA stream after the current transfer has completed, and can optionally generate an
error interrupt to the CPU. This error interrupt can be masked.
Each stream is supported by a dedicated hardware channel, including source and
destination controllers, as well as a FIFO. This enables better latency than a DMA
controller with only a single hardware channel shared between several DMA streams and
simplifies the control logic.
DMA channel priority is fixed. DMA channel 0 has the highest priority and DMA channel 7
has the lowest priority.
If the DMA Controller is transferring data for the lower priority channel and then the higher
priority channel goes active, it completes the number of transfers delegated to the master
interface by the lower priority channel before switching over to transfer data for the higher
priority channel. In the worst case this is as large as a one quadword.
It is recommended that memory-to-memory transactions use the lowest priority channel.
Otherwise other AHB bus masters are prevented from accessing the bus during DMA
Controller memory-to-memory transfer.
A combined interrupt output is generated as an OR function of the individual interrupt
requests of the DMA Controller and is connected to the interrupt controller.
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All information provided in this document is subject to legal disclaimers.
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Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller
Rev. 00.13 — 20 July 2011
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© NXP B.V. 2011. All rights reserved.
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285 of 1164
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