LPC1857FET256,551 NXP Semiconductors, LPC1857FET256,551 Datasheet - Page 241
LPC1857FET256,551
Manufacturer Part Number
LPC1857FET256,551
Description
IC MCU 32BIT 1MB FLASH 256LBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1857FET256,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1857FET256,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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User manual
14.4.25 VADC trigger input multiplexer (VADC_TRIGGER_IN)
14.4.26 Event router input 13 multiplexer (EVENTROUTER_13_IN)
Table 158. SCT CTIN_7 capture input multiplexer (CTIN_7_IN, address 0x400C 705C) bit
Table 159. ADC trigger input multiplexer (VADC_TRIGGER_IN, address 0x400C 7060) bit
Table 160. Event router input 13 multiplexer (EVENTROUTER_13_IN, address 0x400C 7064)
Bit
31:8
Bit
0
1
2
3
7:4
31:8
Bit
0
Symbol
-
Symbol
INV
Symbol
INV
EDGE
SYNCH
PULSE
SELECT
-
description
description
bit description
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
Value Description
0x2
0x3
Value Description
0
1
0
1
0
1
0
1
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
Rev. 00.13 — 20 July 2011
Chapter 14: LPC18xx Global Input Multiplexer Array (GIMA)
Invert input
Not inverted.
Input inverted.
SOF0 (Start-Of-Frame USB0)
SOF1 (Start-Of-Frame USB1)
Reserved
Invert input
Not inverted.
Input inverted.
Enable rising edge detection
No edge detection.
Rising edge detection enabled.
Enable synchronization
Disable synchronization.
Enable synchronization.
Enable single pulse generation.
Disable single pulse generation.
Enable single pulse generation.
Select input. Values 0xA to 0xF are reserved.
GPIO6[28]
GPIO5[3]
Reserved
Reserved
Reserved
MCOB2
CTOUT_0 or T0_MAT0
CTOUT_8 or T2_MAT0
T0_MAT0
T2_MAT0
Reserved
UM10430
© NXP B.V. 2011. All rights reserved.
Reset value
Reset value
Reset value
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