LPC1857FET256,551 NXP Semiconductors, LPC1857FET256,551 Datasheet - Page 581

• Manufacturer Part Number: LPC1857FET256,551
• Description: IC MCU 32BIT 1MB FLASH 256LBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1857FET256,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
23.8 LCD timing diagrams
<Document ID>
User manual
Fig 58. Horizontal timing for STN displays
(panel clock)
(1) The active data lines will vary with the type of STN panel (4-bit, 8-bit, color, mono) and with single or dual frames.
(2) The LCD panel clock is selected and scaled by the LCD controller and used to produce LCDCLK.
(3) The duration of the LCDLP signal is controlled by the HSW field in the TIMH register.
(4) The Polarity of the LCDLP signal is determined by the IHS bit in the POL register.
LCDVD[15:0]
LCDDCLK
(line synch
(panel data)
pixel clock
(internal)
LCDLP
pulse)
LCD_TIMH (HSW)
during LCDLP
suppressed
All information provided in this document is subject to legal disclaimers.
(defined in pixel clocks)
LCD_TIMH (HBP)
horizontal back porch
Rev. 00.13 — 20 July 2011
one horizontal line
one horizontal line of LCD data
16  LCD_TIMH(PPL)  1
Chapter 23: LPC18xx LCD
(defined in pixel clocks)
horizontal front porch
LCD_TIMH (HFP)
UM10430
© NXP B.V. 2011. All rights reserved.
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