LPC1857FET256,551 NXP Semiconductors, LPC1857FET256,551 Datasheet - Page 857

• Manufacturer Part Number: LPC1857FET256,551
• Description: IC MCU 32BIT 1MB FLASH 256LBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1857FET256,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
Table 801. Register overview: I
[1]
<Document ID>
User manual
Name
SCLL
CONCLR
MMCTRL
ADR1
ADR2
ADR3
DATA_
BUFFER
MASK0
MASK1
MASK2
MASK3
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
37.7.1 I
Access Address
R/W
WO
R/W
R/W
R/W
RO
R/W
R/W
R/W
R/W
R/W
The CONSET registers control setting of bits in the CON register that controls operation of
the I
I
2
2
offset
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C
C control register to be set. Writing a zero has no effect.
C Control Set register
2
C interface. Writing a one to a bit of this register causes the corresponding bit in the
2
C1 (base address 0x400E 0000)
Description
SCL Duty Cycle Register Low Half Word. Determines the low time of
the I
frequency generated by an I
mode.
I2C Control Clear Register. When a one is written to a bit of this register,
the corresponding bit in the I
has no effect on the corresponding bit in the I
Monitor mode control register.
I2C Slave Address Register 1. Contains the 7-bit slave address for
operation of the I
mode. The least significant bit determines whether a slave responds to
the General Call address.
I2C Slave Address Register 2. Contains the 7-bit slave address for
operation of the I
mode. The least significant bit determines whether a slave responds to
the General Call address.
I2C Slave Address Register 3. Contains the 7-bit slave address for
operation of the I
mode. The least significant bit determines whether a slave responds to
the General Call address.
Data buffer register. The contents of the 8 MSBs of the DAT shift register
will be transferred to the DATA_BUFFER automatically after every nine
bits (8 bits of data plus ACK or NACK) has been received on the bus.
I2C Slave address mask register 0 . This mask register is associated
with ADR0 to determine an address match. The mask register has no
effect when comparing to the General Call address (‘0000000’).
I2C Slave address mask register 1 . This mask register is associated
with ADR0 to determine an address match. The mask register has no
effect when comparing to the General Call address (‘0000000’).
I2C Slave address mask register 2 . This mask register is associated
with ADR0 to determine an address match. The mask register has no
effect when comparing to the General Call address (‘0000000’).
I2C Slave address mask register 3 . This mask register is associated
with ADR0 to determine an address match. The mask register has no
effect when comparing to the General Call address (‘0000000’).
All information provided in this document is subject to legal disclaimers.
2
C clock. I2nSCLL and nSCLH together determine the clock
Rev. 00.13 — 20 July 2011
2
2
2
C interface in slave mode, and is not used in master
C interface in slave mode, and is not used in master
C interface in slave mode, and is not used in master
2
2
C master and certain times used in slave
…continued
C control register is cleared. Writing a zero
Chapter 37: LPC18xx I2C-bus interface
2
C control register.
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
0x04
-
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
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