LPC1857FET256,551 NXP Semiconductors, LPC1857FET256,551 Datasheet - Page 478
LPC1857FET256,551
Manufacturer Part Number
LPC1857FET256,551
Description
IC MCU 32BIT 1MB FLASH 256LBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1857FET256,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1857FET256,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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22.1 How to read this chapter
22.2 Basic configuration
22.3 Features
<Document ID>
User manual
The Ethernet controller is available on parts LPC1850 and LPC1830.
The Ethernet controller is configured as follows:
Table 400. Ethernet clocking and power control
Ethernet
register
interface clock
Ethernet PHY
clock
Ethernet PHY
clock
•
•
•
•
•
•
•
•
•
•
•
•
UM10430
Chapter 22: LPC18xx Ethernet
Rev. 00.13 — 20 July 2011
See
The Ethernet is reset by the ETHERNET_RST (reset # 22).
The Ethernet interrupt is connected to interrupt slot # 5 in the NVIC, and the is
connected to slot # 8 in the event router.
Set the Ethernet mode to RMII or MII in the CREG6 register in the CREG block (see
Table
10/100 Mbit/s
TCP/IP hardware checksum
IP checksum
DMA support
IEEE 1588 time stamping block
IEEE 1588 advanced time stamp support (IEEE 1588-2008 v2)
Power management remote wake-up frame and magic packet detection
Supports both full-duplex and half-duplex operation
– Supports CSMA/CD Protocol for half-duplex operation.
Table 400
37).
All information provided in this document is subject to legal disclaimers.
Base clock
BASE_M3_CLK CLK_M3_
BASE_PHY_
RX_CLK
BASE_PHY_
TX_CLK
for clocking and power control.
Rev. 00.13 — 20 July 2011
Branch
clock
ETHERNET
-
-
Maximum
frequency
150 MHz
75 MHz
75 MHz
Notes
-
Select the clock pin
ENET_RX_CLK as clock source
for this base clock in the
OUTCLK_7_CTRL register in the
CGU.
Select the clock pin
ENET_TX_CLK as clock source
for this base clock in the
OUTCLK_8_CTRL register in the
CGU.
© NXP B.V. 2011. All rights reserved.
User manual
478 of 1164
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