LPC1857FET256,551 NXP Semiconductors, LPC1857FET256,551 Datasheet - Page 305
LPC1857FET256,551
Manufacturer Part Number
LPC1857FET256,551
Description
IC MCU 32BIT 1MB FLASH 256LBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1857FET256,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1857FET256,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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User manual
18.6.11 Command Argument Register (CMDARG)
Table 234. Interrupt Mask Register (INTMASK, address 0x4000 4024) bit description
Table 235. Command Argument Register (CMDARG, address 0x4000 4028) bit description
Bit
5
6
7
8
9
10
11
12
13
14
15
31:16
Bit
31:0
Symbol
CMD_ARG
Symbol
RXDR
RCRC
DCRC
RTO
DRTO
HTO
FRUN
HLE
SBE
ACD
EBE
SDIO_INT_MASK Mask SDIO interrupts One bit for each card. Bit[31]
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Description
Value indicates command argument to be passed to card. 0
Description
Receive FIFO data request. Bits used to mask unwanted
interrupts. Value of 0 masks interrupt; value of 1 enables
interrupt.
Response CRC error. Bits used to mask unwanted
interrupts. Value of 0 masks interrupt; value of 1 enables
interrupt.
Data CRC error. Bits used to mask unwanted interrupts.
Value of 0 masks interrupt; value of 1 enables interrupt.
Response time-out. Bits used to mask unwanted
interrupts. Value of 0 masks interrupt; value of 1 enables
interrupt.
Data read time-out. Bits used to mask unwanted interrupts.
Value of 0 masks interrupt; value of 1 enables interrupt.
Data starvation-by-host time-out (HTO) /Volt_switch_int.
Bits used to mask unwanted interrupts. Value of 0 masks
interrupt; value of 1 enables interrupt.
FIFO underrun/overrun error. Bits used to mask unwanted
interrupts. Value of 0 masks interrupt; value of 1 enables
interrupt.
Hardware locked write error. Bits used to mask unwanted
interrupts. Value of 0 masks interrupt; value of 1 enables
interrupt.
Start-bit error. Bits used to mask unwanted interrupts.
Value of 0 masks interrupt; value of 1 enables interrupt.
Auto command done. Bits used to mask unwanted
interrupts. Value of 0 masks interrupt; value of 1 enables
interrupt.
End-bit error (read)/Write no CRC. Bits used to mask
unwanted interrupts. Value of 0 masks interrupt; value of 1
enables interrupt.
corresponds to card[15], and bit[16] corresponds to
card[0]. When masked, SDIO interrupt detection for that
card is disabled. A 0 masks an interrupt, and 1 enables an
interrupt. In MMC-Ver3.3-only mode, these bits are always
0.
Chapter 18: LPC18xx SD/MMC interface
UM10430
© NXP B.V. 2011. All rights reserved.
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