LPC1857FET256,551 NXP Semiconductors, LPC1857FET256,551 Datasheet - Page 486

• Manufacturer Part Number: LPC1857FET256,551
• Description: IC MCU 32BIT 1MB FLASH 256LBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1857FET256,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
<Document ID>
User manual
22.6.4 MAC Hash table low register
22.6.5 MAC MII Address register
If the Hash Table register is configured to be double-synchronized to the (G)MII clock
domain, the synchronization is triggered only when Bits[31:24] (in Little-Endian mode) or
Bits[7:0] (in Big-Endian mode) of the Hash Table High/Low registers are written to. Please
note that consecutive writes to these register should be performed only after at least 4
clock cycles in the destination clock domain when double synchronization is enabled.
The Hash Table High register contains the higher 32 bits of the Hash table.
Table 405. MAC Hash table high register (MAC_HASHTABLE_HIGH, address 0x4001 0008) bit
The Hash Table Low register contains the lower 32 bits of the Hash table.
Table 406. MAC Hash table low register (MAC_HASHTABLE_LOW, address 0x4001 0008) bit
The MII Address register controls the management cycles to the external PHY through the
management interface.
Bit
31:0
Bit
31:0
Symbol
HTH
Symbol
HTL
description
description
All information provided in this document is subject to legal disclaimers.
Description
Hash table high
This field contains the upper 32 bits of Hash table.
Description
Hash table low
This field contains the upper 32 bits of Hash table.
Rev. 00.13 — 20 July 2011
Chapter 22: LPC18xx Ethernet
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
Reset
value
0
486 of 1164
Access
R/W
Access
R/W