UPD78F0988AGC-8BS Renesas Electronics America, UPD78F0988AGC-8BS Datasheet - Page 65

• Manufacturer Part Number: UPD78F0988AGC-8BS
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0988AGC-8BS

• Lead Free Status / Rohs Status: Supplier Unconfirmed

3.2 Processor Registers
3.2.1 Control registers
memory. The control registers include the program counter (PC), program status word (PSW), and stack pointer (SP).
The PD780988 Subseries is provided with the following processor registers.
Each of these registers has a dedicated function such as to control the program sequence, status, and stack
(1) Program counter (PC)
(2) Program status word (PSW)
The program counter is a 16-bit register that holds the address of the program to be executed next.
The contents of this register are automatically incremented according to the number of bytes of the instruction
to be fetched when a normal operation is performed. When a branch instruction is executed, immediate data
or the contents of a register are set to the program counter.
When the RESET signal is input, the value of the reset vector table at addresses 0000H and 0001H is set
to the program counter.
The program status word is an 8-bit register consisting of flags that are set or reset as a result of instruction
execution.
The contents of the program status word are automatically pushed to the stack when an interrupt request is
generated or when the PUSH PSW instruction is executed, and are automatically popped from the stack when
the RETB, RETI, or POP PSW instruction is executed.
The contents of the program status word are set to 02H when the RESET signal is input.
(a) Interrupt enable flag (IE)
(b) Zero flag (Z)
PC
This flag controls acknowledgement of an interrupt request by the CPU.
When IE = 0, all interrupt requests except the non-maskable interrupt are disabled (DI status).
When IE = 1, interrupts are enabled (EI status). At this time, acknowledgement of interrupt requests is
controlled with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources, and
a priority specification flag.
The interrupt enable flag is reset to 0 when the DI instruction is executed or when an interrupt request
is acknowledged, and set to 1 when the EI instruction is executed.
This flag is set to 1 when the result of an operation performed is 0; otherwise, it is reset to 0.
PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
15
PSW
Figure 3-14. Program Status Word Configuration
IE
7
Figure 3-13. Program Counter Configuration
Z
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U13029EJ7V1UD
RBS1
AC
RBS0
0
ISP
CY
0
0
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