UPD78F0988AGC-8BS Renesas Electronics America, UPD78F0988AGC-8BS Datasheet - Page 249

• Manufacturer Part Number: UPD78F0988AGC-8BS
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0988AGC-8BS

• Lead Free Status / Rohs Status: Supplier Unconfirmed

framing/overrun error)
Parity error
Framing error
Overrun error
(On occurrence of
Receive Error
(e) Receive errors
(On occurrence
of parity error)
RxD0n (Input)
INTSER0
INTSER0
INTSRn
The three types of errors during receive operations are the parity error, framing error and overrun error.
With the UART00, setting the data receive result error flag in asynchronous serial interface status register
0 (ASIS00) generates a receive error interrupt request (INTSER0). The receiver error interrupt request
is generated before the receive complete interrupt request (INTSR0). With the UART01, the receiver error
interrupt request is not generated. Table 12-5 shows the causes of receive errors.
Reading the data in ASIS0n makes it possible to ascertain what error has occurred during reception (see
Figures 12-14 and 12-15).
The contents of ASIS0n are reset (0) by reading receive buffer register n (RXB0n) or receiving the next
data (if there is an error in the next data, the corresponding error flag is set).
Notes 1. INTSRn is not generated if a receive error occurs when the ISRM0n bit is set (1).
Cautions 1. The contents of ASIS0n are reset (to 0) by reading receive buffer register n (RXB0n)
Remark n = 0, 1
Note 1
Note 2
Note 2
2. The receive error interrupt request is not generated with UART01.
Transmission-time parity specification and reception data parity do not match
Stop bit not detected
Reception of next data is completed before data is read from receive buffer register
2. Receive buffer register n (RXB0n) must be read even if a receive error has occurred.
or receiving the next data. To ascertain the error contents, ASIS0n must be read
before reading RXB0n.
If RXB0n is not read, an overrun error will occur when the next data is received, and
the receive error state will continue indefinitely.
CHAPTER 12 SERIAL INTERFACES UART00 AND UART01
START
Figure 12-15. Receive Error Timing
Table 12-5. Receive Error Causes
User’s Manual U13029EJ7V1UD
D0
D1
Cause
D2
D6
D7
Parity
STOP
ASIS0n Value
04H
02H
01H
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