UPD78F0988AGC-8BS Renesas Electronics America, UPD78F0988AGC-8BS Datasheet - Page 272

• Manufacturer Part Number: UPD78F0988AGC-8BS
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0988AGC-8BS

• Lead Free Status / Rohs Status: Supplier Unconfirmed

14.4 Interrupt Servicing Operation
14.4.1 Non-maskable interrupt request acknowledgement operation
It is not subject to interrupt priority control and takes precedence over all other interrupts.
word (PSW) and program counter (PC), in that order, the IE flag and ISP flag are reset to 0, the contents of the vector
table are loaded to the PC, and then program execution branches.
executed, the interrupt request is acknowledged when the current execution of the non-maskable interrupt service
program is complete (after the RETI instruction has been executed) and one instruction in the main routine has been
executed. If two or more new non-maskable interrupt requests are generated while the non-maskable interrupt service
program is being executed, only one non-maskable interrupt request is acknowledged after execution of the non-
maskable interrupt service program is complete.
9 shows the timing of non-maskable interrupt request acknowledgement, and Figure 14-10 shows the acknowledgement
operation when multiple non-maskable interrupt requests are generated.
270
Symbol
(6) Program status word (PSW)
The non-maskable interrupt request is unconditionally acknowledged even when interrupt requests are disabled.
When the non-maskable interrupt request is acknowledged, the contents are saved to the stack, program status
If a new non-maskable interrupt request is generated while the non-maskable interrupt service program is being
Figure 14-8 shows the flowchart from non-maskable interrupt request generation to acknowledgement, Figure 14-
PSW
The program status word is a register that holds the instruction execution result and current status of interrupt
request. An IE flag that enables/disables the maskable interrupts and an ISP flag that controls multiple
interrupts processing are mapped to this register.
This register can be read or written in 8-bit units. In addition, it can also be manipulated by using a bit
manipulation instruction or dedicated instructions (EI and DI).
acknowledged, and when the BRK instruction is executed, the contents of the PSW are automatically saved
to the stack. At this time, the IE flag is reset to 0. If a maskable interrupt request has been acknowledged,
the contents of the priority flag of that interrupt are transferred to the ISP flag. The contents of the PSW can
also be saved to the stack by the PUSH PSW instruction, and restored from the stack by RETI, RETB, or POP
PSW instruction.
RESET input sets the PSW to 02H.
IE
7
Z
6
RBS1
5
Figure 14-7. Configuration of Program Status Word
AC
4
RBS0
CHAPTER 14 INTERRUPT FUNCTIONS
3
User’s Manual U13029EJ7V1UD
2
0
ISP
1
CY
0
ISP
IE
0
1
0
1
After reset
Used when normal instruction is executed
02H
Interrupt with higher priority is processed (interrupt
with lower priority is disabled).
Interrupt is not acknowledged, or interrupt with lower
priority is processed (all maskable interrupts are
enabled).
Disables
Enables
Interrupt request acknowledge enable/disable
Priority of interrupt currently processed
When a vectored interrupt request is