UPD78F0988AGC-8BS Renesas Electronics America, UPD78F0988AGC-8BS Datasheet - Page 139

• Manufacturer Part Number: UPD78F0988AGC-8BS
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0988AGC-8BS

• Lead Free Status / Rohs Status: Supplier Unconfirmed

(8) Timer operation
(9) Capture operation
(10) Compare operation
(11) Edge detection
<1> Even if 16-bit timer counter 0n (TM0n) is read, the value is not captured in 16-bit capture/compare register
<2> Regardless of the operation mode of the CPU, if the timer is stopped, the noise of the external interrupt
Remark n = 0, 1
<1> When the valid edge of TI00n (n = 0, 1) is specified for the count clock, the capture register that specified
<2> A capture operation is not performed when both the rising and falling edges are specified for the TI00n valid
<3> In order to ensure the capture operation, a pulse longer than two clocks of the count clock specified by
<4> Capture operations start at the falling edge of the count clock. However, interrupt request input (INTTM00n)
Remark n = 0, 1
<1> If values are written to 16-bit capture/compare registers 00n and 01n (CR00n, CR01n) at the timing when
<2> CR00n and CR01n set in the compare mode cannot perform a capture operation even if the capture trigger
Remark n = 0, 1
<1> When the TI00n pin or the TI01n pin is high level immediately after system reset, and if the rising edge or
<2> A different sampling clock for noise elimination is used when the TI00n pin valid edge is used for the count
Remark n = 0, 1
01n (CR01n).
request input is not removed.
TI00n as the trigger cannot perform the capture operation normally.
edge.
prescaler mode register 0n (PRM0n) is required for a capture trigger.
starts at the rising edge of the count clock.
the set values of CR00n and CR01n and the count value of 16-bit timer counter 0n (TM0n) match generating
INTTM00n and INTTM01n, INTTM00n and INTTM01n may not be generated. Therefore, do not write values
to CR00n and CR01n repeatedly even if the values are the same.
is input.
both edges are specified as the valid edge of the TI00n pin or the TI01n pin, then the rising edge is detected
immediately after operation of 16-bit timer counter 0n (TM0n) is enabled. Be careful when the TI00n pin
or the TI01n pin is pulled up. When operation is enabled again after once being stopped, the rising edge
cannot be detected.
clock and when it is used for capture trigger. In the former case, a count clock of f
latter case the count clock specified by prescaler mode register 0n (PRM0n) is used for sampling. A capture
operation is only performed when sampling is performed at the above described sampling clock and when
a valid level is detected twice, thus eliminating noise with a short-pulse width.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER
User’s Manual U13029EJ7V1UD
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is used, and in the
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