UPD78F0988AGC-8BS Renesas Electronics America, UPD78F0988AGC-8BS Datasheet - Page 180

• Manufacturer Part Number: UPD78F0988AGC-8BS
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0988AGC-8BS

• Lead Free Status / Rohs Status: Supplier Unconfirmed

9.5 Operation of Watchdog Timer
9.5.1 Operation as watchdog timer
(WDTM) is set to 1.
watchdog timer clock select register (WDCS). By setting bit 7 (RUN) of WDTM to 1, the watchdog timer is started.
Set RUN to 1 within the set loop detection time interval after the watchdog timer has been started. By setting RUN
to 1, the watchdog timer can be cleared and made to start counting. If RUN is not set to 1 and the loop detection
time is exceeded, the system is reset or a non-maskable interrupt request is generated by the value of bit 3 (WDTM3)
of WDTM.
to 1 before entering the STOP mode to clear the watchdog timer, and then execute the STOP instruction.
178
The watchdog timer detects an inadvertent program loop when bit 4 (WDTM4) of the watchdog timer mode register
The loop detection time interval of the watchdog timer can be selected by bits 0 to 2 (WDCS0 to WDCS2) of the
The watchdog timer continues operation in the HALT mode, but stops in the STOP mode. Therefore, set RUN
Cautions 1. The actual loop detection time may be up to 2
Note Expanded-specification products only.
Remark f
WDCS22 WDCS21 WDCS20 Loop Detection Time
2. The count operation of the watchdog timer is stopped when the subsystem clock is selected
0
0
0
0
1
1
1
1
as the CPU clock.
X
: System clock oscillation frequency
0
0
1
1
0
0
1
1
Table 9-4. Loop Detection Time of Watchdog Timer
0
1
0
1
0
1
0
1
CHAPTER 9 WATCHDOG TIMER
2
2
2
2
2
2
2
2
12
13
14
15
16
17
18
20
User’s Manual U13029EJ7V1UD
1/f
1/f
1/f
1/f
1/f
1/f
1/f
1/f
X
X
X
X
X
X
X
X
At f
X
341.3 s
682.6 s
1.36 ms
2.73 ms
5.46 ms
10.9 ms
21.8 ms
87.3 ms
= 12 MHz
8
/f
X
seconds shorter than the set time.
Note
At f
X
125.1 ms
488.8 s
977.6 s
1.96 ms
3.91 ms
7.82 ms
15.6 ms
31.3 ms
= 8.38 MHz