UPD78F0988AGC-8BS Renesas Electronics America, UPD78F0988AGC-8BS Datasheet - Page 233

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UPD78F0988AGC-8BS

Manufacturer Part Number
UPD78F0988AGC-8BS
Description
Manufacturer
Renesas Electronics America
Datasheet

Specifications of UPD78F0988AGC-8BS

Lead Free Status / Rohs Status
Supplier Unconfirmed
(3) Baud rate generator control registers 0, 1 (BRGC00, BRGC01)
Notes 1. Even if the stop bit length is set to 2 bits using bit 2 (SL01) of asynchronous serial interface mode
BRGC00 and BRGC01 are the registers that set the serial clock of the asynchronous serial interface.
These registers are set by an 8-bit memory manipulation instruction.
RESET input clears these registers to 00H.
ASIS01
Symbol
2. If an overrun error occurs, be sure to read receive buffer register 1 (RXB01). Until RXB01 is read,
Figure 12-8. Format of Asynchronous Serial Interface Status Register 1
register 1 (ASIM01), only 1 stop bit is detected during reception.
an overrun error persistently occurs each time data is received.
OVE01
PE01
FE01
7
0
0
1
0
1
0
1
CHAPTER 12 SERIAL INTERFACES UART00 AND UART01
Parity error does not occur.
Parity error occurs (transmit data parity
specification and receive data parity do not
match).
Overrun error does not occur.
Overrun error occurs
completed before data is read from receive
buffer register).
Framing error does not occur.
Framing error occurs
(stop bit not detected).
6
0
5
0
Framing error flag
Overrun error flag
Parity error flag
4
0
User’s Manual U13029EJ7V1UD
Note 2
Note 1
3
0
(Next receive
PE01 FE01 OVE01
2
1
0
Address
FFA9H
After reset
00H
R/W
R
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