WG82577LM S LGWR Intel, WG82577LM S LGWR Datasheet - Page 85
WG82577LM S LGWR
Manufacturer Part Number
WG82577LM S LGWR
Description
Manufacturer
Intel
Datasheet
1.WG82577LM_S_LGWR.pdf
(195 pages)
Specifications of WG82577LM S LGWR
Lead Free Status / Rohs Status
Supplier Unconfirmed
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Programmer’s Visible State—82577 GbE PHY
Table 56.
Table 57.
Table 58.
Table 59.
In-Band Control PHY Address 01, Page 770, Register 18
1. All in-band timeouts are multiplied by 1000 while in SMBus mode.
PCIe Diagnostic PHY Address 01, Page 770, Register 20
1. All in-band timeouts are multiplied by 1000 while in SMBus mode.
Timeouts PHY Address 01, Page 770, Register 21
1. All in-band timeouts are multiplied by 1000 while in SMBus mode.
PCIe Kstate Minimum Duration Timeout PHY Address 01, Page 770, Register
23
1. All in-band timeouts are multiplied by 1000 while in SMBus mode.
Link status transmit timeout
pcie_pad_use_dis
Max retries
Reserved
In-band status acknowledge
timeout
Reserved
Reserved
Reserved
Reserved
EI_min_dur timeout
1
Name
Name
Name
Name
0x00
0x10
0x5
0b
0x7
0x55
0x04
0000b
010100b
010100b
Default
Default
Default
Default
15:8
7
6:0
15:8
7:0
15:12
11:6
5:0
15:5
4:0
Bits
Bits
Bits
Bits
Reserved, write as read.
These bits define the minimum time the 82577
stays in electrical idle state once entered (each
bit represents 80 ns).
Link status retransmission period in tens of
microseconds.
Disables 1000 Mb/s in-band messages during
packets in 10/100 Mb/s mode.
Maximum retries when not receiving an
acknowledge to an in-band message.
Reserved, write as read.
Timeout in microseconds for receiving an
acknowledge for an in-band status message.
Reserved, write as read.
Reserved
Reserved
1
Description
Description
Description
Description
1
1
R/W
R/W
R/W
R/W
R/W
RWP
R/W
R/W
RWP
R/W
Type
Type
Type
Type
78
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