WG82577LM S LGWR Intel, WG82577LM S LGWR Datasheet - Page 125

• Manufacturer Part Number: WG82577LM S LGWR
• Manufacturer: Intel

Specifications of WG82577LM S LGWR

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Intel
®
5 Series Express Chipset MAC Programming Interface—82577 GbE PHY
0x000C0
0x000C4
0x000C8
0x000D0
0x000D8
0x000E0
0x00100
0x00104
0x02008
0x02170
0x02160
0x02168
0x02800
0x02804
0x02808
0x02810
0x02818
0x02820
0x02828
0x0282C
0x02C00
0x02C08
0x05000
0x05008
0x05200-0x0527C
0x05400 + 8*n
(n=0…6)
0x05404 + 8*n
(n=0…6)
0x05438 + 8*n
(n=0…3)
0x0543C + 8*n
(n=0…2)
0x05454
0x05818
0x05C00 + 4*n
(n=0…31)
0x05C80 + 4*n
(n=0…9)
Offset
Mask - IAM
MRQC
IMC
RSRPD
RAL
RAH
SRAL
SRAH
RETA
RSSRK
ICR
ITR
ICS
IMS
RCTL
RCTL1
ERT
PSRCTL
FCRTL
FCRTH
RDBAL
RDBAH
RDLEN
RDH
RDT
RDTR
RXDCTL
RADV
RAID
RXCSUM
RFCTL
MTA[31:0]
SHRAH[3]
Abbreviation
Interrupt Register Descriptions
Receive Register Descriptions
Interrupt Cause Read Register
Interrupt Throttling Register
Interrupt Cause Set Register
Interrupt Mask Set/Read Register
Interrupt Mask Clear Register
Interrupt Acknowledge Auto
Receive Control Register
Receive Control Register 1
Early Receive Threshold
Packet Split Receive Control Register
Flow Control Receive Threshold Low
Flow Control Receive Threshold High
Receive Descriptor Base Address Low
Queue
Receive Descriptor Base Address High
Queue
Receive Descriptor Length Queue
Receive Descriptor Head Queue
Receive Descriptor Tail Queue
Interrupt Delay Timer (Packet Timer)
Receive Descriptor Control
Receive Interrupt Absolute Delay Timer
Receive Small Packet Detect Interrupt
Receive ACK Interrupt Delay Register
Receive Checksum Control
Receive Filter Control Register
Multicast Table Array
Receive Address Low
Receive Address High
Shared Receive Address Low
Shared Receive Address High 0…2
Shared Receive Address High 3
Multiple Receive Queues Command
Register
Redirection Table
Random Key Register
Name
WC
RW
RC/
RW
WO
RW
WO
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
10.2.1.2.1
10.2.1.2.2
10.2.1.2.3
10.2.1.2.4
10.2.1.2.5
10.2.1.2.6
10.2.1.3.1
10.2.1.3.2
10.2.1.3.3
10.2.1.3.4
10.2.1.3.5
10.2.1.3.6
10.2.1.3.7
10.2.1.3.8
10.2.1.3.9
10.2.1.3.10
10.2.1.3.11
10.2.1.3.12
10.2.1.3.13
10.2.1.3.14
10.2.1.3.15
10.2.1.3.16
10.2.1.3.17
10.2.1.3.18
10.2.1.3.19
10.2.1.3.20
10.2.1.3.21
10.2.1.3.22
10.2.1.3.23
10.2.1.3.24
10.2.1.3.25
10.2.1.3.26
10.2.1.3.27
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