WG82577LM S LGWR Intel, WG82577LM S LGWR Datasheet - Page 156

• Manufacturer Part Number: WG82577LM S LGWR
• Manufacturer: Intel

Specifications of WG82577LM S LGWR

• Lead Free Status / Rohs Status: Supplier Unconfirmed

10.2.1.3.15 Receive Small Packet Detect Interrupt- RSRPD (0x02C00; RW)
10.2.1.3.16 Receive ACK Interrupt Delay Register - RAID (0x02C08; RW)
10.2.1.3.17 Receive Checksum Control - RXCSUM (0x05000; RW)
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Setting this register to zero disables the absolute timer mechanism (the RDTR register
should be used with a value of zero to cause immediate interrupts for all receive
packets).
Receive interrupts due to a Receive Packet Timer (RDTR) expiration cancels a pending
RADV interrupt. If enabled, the RADV countdown timer is reloaded but halted, so as to
avoid generation of a spurious second interrupt after the RDTR has been noted.
If an immediate (non-scheduled) interrupt is desired for any received ACK frame, the
ACK_DELAY should be set to zero.
The Receive Checksum Control register controls the receive checksum offloading
features of the MAC. The MAC supports the offloading of three receive checksum
calculations: the packet checksum, the IP header checksum, and the TCP/UDP
checksum.
PCSD: The packet checksum and IP Identification fields are mutually exclusive with the
RSS hash. Only one of the two options is reported in the Rx descriptor. The
RXCSUM.PCSD affect is shown in the following table:
11:0
31:12
15:0
31:16
7:0
8
9
11:10
12
13
14
31:15
Bits
Bits
Bits
RW
RO
RW
RO
RW
RW
RW
RO
RW
RW
RW
RO
Type
Type
Type
0x0
X
0x0
0x0
0x00
1b
1b
00b
0b
0b
0b
0x0
Reset
Reset
Reset
82577 GbE PHY—Intel
SIZE. If the interrupt is enabled any receive packet of size <= SIZE asserts an
interrupt. SIZE is specified in bytes and includes the headers and the CRC. It does
not include the VLAN header in size calculation if it is stripped.
Reserved.
ACK_DELAY. ACK delay timer measured in increments of 1.024 ms. When the
Receive ACK frame detect interrupt is enabled in the IMS register, ACK packets
being received uses a unique delay timer to generate an interrupt. When an ACK
is received, an absolute timer loads to the value of ACK_DELAY. The interrupt
signal is set only when the timer expires. If another ACK packet is received while
the timer is counting down, the timer is not reloaded to ACK_DELAY.
Reserved.
Packet Checksum Start (PCSS).
IP Checksum Offload Enable (IPOFL).
TCP/UDP Checksum Offload Enable (TUOFL).
Reserved.
IP Payload Checksum Enable (IPPCSE).
Packet Checksum Disable (PCSD).
Reserved.
Reserved.
®
5 Series Express Chipset MAC Programming Interface
Description
Description
Description